公开(公告)号：US20150357477A1

公开(公告)日：2015-12-10

申请号：US14298000

申请日：2014-06-06

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang ,  Walter Kleemeier

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/41766 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/4975 ,  H01L29/78603 ,  H01L29/78648

Abstract: An integrated circuit transistor is formed on and in a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region epitaxially grown above the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate is preferably of the silicon on insulator (SOI) type.

Abstract translation: 集成电路晶体管形成在衬底上和衬底中。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括在源极（或漏极）触点上方外延生长的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底优选为绝缘体上硅（SOI）型。

公开(公告)号：US20150357439A1

公开(公告)日：2015-12-10

申请号：US14295618

申请日：2014-06-04

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Ruilong XIE ,  Xiuyu CAI ,  Chun-chen YEH

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/785

Abstract: A method for making a semiconductor device may include forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins, and forming regions of a first dielectric material between the laterally spaced-apart semiconductor fins. The method may further include selectively removing at least one intermediate semiconductor fin from among the plurality of semiconductor fins to define at least one trench between corresponding regions of the first dielectric material, and forming a region of a second dielectric material different than the first dielectric in the at least one trench to provide at least one isolation pillar between adjacent semiconductor fins.

Abstract translation: 制造半导体器件的方法可以包括在衬底之上形成多个横向间隔开的半导体鳍片，以及在横向间隔开的半导体鳍片之间形成第一电介质材料的区域。 该方法还可以包括：从多个半导体鳍片中选择性地移除至少一个中间半导体鳍片，以限定第一介电材料的相应区域之间的至少一个沟槽，以及形成与第一电介质不同的第二电介质材料的区域 所述至少一个沟槽用于在相邻的半导体鳍片之间提供至少一个隔离柱。

公开(公告)号：US20150357243A1

公开(公告)日：2015-12-10

申请号：US14296818

申请日：2014-06-05

Applicant: STMICROELECTRONICS. INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Xiuyu CAl ,  Ruilong XIE ,  Chun-chen YEH

IPC: H01L21/8238 ,  H01L27/12 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/786 ,  H01L29/78684

Abstract: A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states.

Abstract translation: 提供一种制造半导体器件的方法。 在热处理之后，用拉伸应变诱导材料形成凸起的源极和漏极区域以形成源极漏极延伸区域，从而将应变诱导材料保持在期望的替代状态。

公开(公告)号：US20150351234A1

公开(公告)日：2015-12-03

申请号：US14294875

申请日：2014-06-03

Applicant: STMicroelectronics, Inc.

Inventor： Rammil Seguido ,  Frederick Ray Gomez ,  Emmanuel Angeles

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H05K3/30

CPC classification number: H05K1/0296 ,  H01L23/66 ,  H01L25/0652 ,  H01L2224/48091 ,  H01L2224/73265 ,  H05K1/0271 ,  H05K1/111 ,  H05K1/181 ,  H05K3/305 ,  H05K2201/09236 ,  H05K2201/09781 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10719 ,  H05K2201/10977 ,  H05K2203/049 ,  Y10T29/49146 ,  H01L2924/00014

Abstract: Delamination of stacked integrated circuit die configurations on printed circuit boards is avoided by providing a metal trace support structure underneath the die stack. The metal trace support structure features substantially equally spaced thin metal traces in place of a contiguous metal plate which has been used in the past. Spaced apart thin metal traces are less vulnerable to thermal expansion than a metal plate which has a large thermal mass. The metal traces still provide structural stability, while preventing delamination of the die stack configuration during thermal processing. A method of attaching a bridge die stack configuration to a printed circuit board by adhering a die attach film to a field of metal traces is demonstrated. In addition, the electrical and structural integrity of the bridge die stack formed with a metal trace support structure is confirmed with test results.

Abstract translation: 通过在管芯堆叠下方提供金属迹线支撑结构，可以避免印刷电路板上的堆叠集成电路管芯结构的分层。 金属迹线支撑结构具有基本相等间隔的细金属迹线，代替过去使用的连续金属板。 分隔开的薄金属迹线比具有大热质量的金属板不易受热膨胀。 金属迹线仍然提供结构稳定性，同时防止热处理期间芯片堆叠配置的分层。 证明了通过将管芯附着膜粘附到金属痕迹的领域将桥模组叠构造附着到印刷电路板的方法。 此外，用测试结果证实了由金属迹线支撑结构形成的桥模组的电气和结构完整性。

公开(公告)号：US20150348851A1

公开(公告)日：2015-12-03

申请号：US14822959

申请日：2015-08-11

Applicant: STMicroelectronics, Inc.

Inventor： Ronald K. Sampson ,  Nicolas Loubet

IPC: H01L21/84 ,  H01L29/10 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/3081 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.

Abstract translation: 将半导体材料图案化以限定与底层基板绝缘的细长翅片。 多晶硅半导体材料沉积在细长翅片之上并在细长翅片之间，并且被图案化以限定延伸到在晶体管沟槽处垂直交叉在细长翅片上的细长门。 侧壁间隔件形成在细长门的侧壁上。 位于细长门之间的细长翅片的部分与下面的绝缘体一起被去除以暴露下面的基底。 然后在细长门之间的位置从下面的衬底外延生长一个或多个半导体材料层。 一个或多个半导体材料层可以包括未掺杂的外延层和上覆的掺杂外延层。 外延材料限定晶体管的源极或漏极。

公开(公告)号：US09202920B1

公开(公告)日：2015-12-01

申请号：US14447727

申请日：2014-07-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Chun-chen Yeh ,  Ruilong Xie ,  Xiuyu Cai

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848

Abstract: Methods and structures for forming short-channel finFETs with vertical and abrupt source and drain junctions are described. During fabrication, source and drain regions of the finFET may be recessed vertically and laterally under gate spacers. A buffer having a high dopant density may be formed on vertical sidewalls of the channel region after recessing the fin. Raised source and drain structures may be formed at the recessed source and drain regions. The raised source and drain structures may impart strain to the channel region.

Abstract translation: 描述了用于形成具有垂直和突然的源极和漏极结的短沟道finFET的方法和结构。 在制造期间，finFET的源极和漏极区域可以在栅极间隔物下方垂直和横向地凹陷。 具有高掺杂浓度的缓冲器可以在凹陷鳍片之后形成在沟道区域的垂直侧壁上。 可以在凹陷的源极和漏极区域形成升高的源极和漏极结构。 升高的源极和漏极结构可能对沟道区域施加应变。

公开(公告)号：US09190517B2

公开(公告)日：2015-11-17

申请号：US14518590

申请日：2014-10-20

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicolas Loubet ,  Douglas Latulipe ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/417 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823425 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/4958 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method for making a semiconductor device includes forming at least one gate stack on a layer comprising a first semiconductor material and etching source and drain recesses adjacent the at least one gate stack. The method further includes shaping the source and drain recesses to have a vertical side extending upwardly from a bottom to an inclined extension adjacent the at least one gate stack.

Abstract translation: 制造半导体器件的方法包括在包括第一半导体材料的层上形成至少一个栅极堆叠，以及邻近所述至少一个栅极堆叠的蚀刻源极和漏极凹陷。 该方法进一步包括成形源极和漏极凹槽以具有从底部向上延伸到与所述至少一个栅极堆叠相邻的倾斜延伸部的垂直侧。

公开(公告)号：US20150325686A1

公开(公告)日：2015-11-12

申请号：US14272660

申请日：2014-05-08

Applicant: SOITEC ,  STMICROELECTRONICS, INC.

Inventor： Frédéric Allibert ,  Pierre Morin

IPC: H01L29/66 ,  H01L29/205 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02614 ,  H01L21/02694 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/205

Abstract: Methods of fabricating semiconductor structures involve the formation of fins for finFET transistors having different stress/strain states. Fins of one stress/strain state may be employed to form n-type finFETS, while fins of another stress/strain state may be employed to form p-type finFETs. The fins having different stress/strain states may be fabricated from a common layer of semiconductor material. Semiconductor structures and devices are fabricated using such methods.

Abstract translation: 制造半导体结构的方法涉及形成具有不同应力/应变状态的finFET晶体管的翅片。 可以使用一个应力/应变状态的芯来形成n型finFET，而可以采用另一个应力/应变状态的翅片来形成p型finFET。 具有不同应力/应变状态的翅片可以由公共半导体材料层制造。 使用这种方法制造半导体结构和器件。

公开(公告)号：US20150325597A1

公开(公告)日：2015-11-12

申请号：US14802996

申请日：2015-07-17

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L27/12 ,  H01L27/092 ,  H01L27/112 ,  H01L29/78 ,  H01L23/528 ,  H01L27/11 ,  H01L29/161

CPC classification number: H01L27/1211 ,  H01L21/266 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/11213 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7838 ,  H01L29/7849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

Abstract translation: 适用于SRAM存储器阵列的单栅极和双栅极FinFET器件具有由半导体衬底上的单个邻接层的部分形成的各自的鳍片，源极区域和漏极区域，因此不需要STI。 FinFET的一对可以配置为从属栅极器件，其中相邻通道由公共栅极控制，或者作为独立栅极器件，其中一个通道由两个栅极控制。 耦合多个FinFET器件的金属互连由与栅电极相同的材料制成。 这种结构和材料的共同点有助于降低制造高密度存储器阵列的成本。

公开(公告)号：US09177903B2

公开(公告)日：2015-11-03

申请号：US13853784

申请日：2013-03-29

Applicant: STMicroelectronics, Inc.

Inventor： Bernie Chrisanto Ang ,  Bryan Christian Bacquian

IPC: H01L21/00 ,  H01L23/498 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A method of assembling a multi-chip electronic device into a thin electronic package entails inverting a flip-chip die arrangement over a hollow substrate, stacking additional dies on the hollow substrate to form a multi-chip electronic device, and encapsulating the multi-chip electronic device. Containment of the encapsulant can be achieved by joining split substrate portions, or by reinforcing a hollow unitary substrate, using a removable adhesive film. Use of the removable adhesive film facilitates surrounding the multi-chip electronic device with the encapsulant. The adhesive film can also prevent encapsulant from creeping around the substrate to an underside of the substrate that supports solder ball pads for subsequent attachment to a ball grid array (BGA) or a land grid array (LGA).

Abstract translation: 将多芯片电子器件组装成薄电子封装的方法需要在中空衬底上反转倒装芯片布置，在中空衬底上堆叠另外的管芯以形成多芯片电子器件，并且封装多芯片 电子设备。 密封剂的封闭可以通过使用可移除的粘合剂膜连接分离的衬底部分或通过加强中空的整体衬底来实现。 使用可移除的粘合膜有助于用密封剂围绕多芯片电子器件。 粘合剂膜还可以防止密封剂在衬底周围爬行到支撑焊球垫的衬底的下侧，用于随后附接到球栅阵列（BGA）或焊盘栅阵列（LGA）。