公开(公告)号：US10015449B2

公开(公告)日：2018-07-03

申请号：US14514132

申请日：2014-10-14

Applicant: STMicroelectronics, Inc.

Inventor： Oleg Logvinov ,  James D. Allen

IPC: H04N7/18 ,  H04N5/232

CPC classification number: H04N7/181 ,  H04N5/23203 ,  H04N5/23206

Abstract: Embodiments of the present disclosure include a system and a method of accessing a system. An embodiment is a system including an imaging system including a controller and a first camera, the controller having a communication connection configured to transmit or receive content or control signals, and a mobile device including a second camera, the mobile device having a communication interface configured to transmit or receive content or control signals with the controller, the controller being configured to compare images from the first and second cameras to allow access to the controller from the mobile device.

公开(公告)号：US20180167016A1

公开(公告)日：2018-06-14

申请号：US15428847

申请日：2017-02-09

Applicant: STMicroelectronics, Inc.

Inventor： Cheng Peng ,  Robert Krysiak

IPC: H02P29/60 ,  H02P27/08

CPC classification number: H02P29/60 ,  H02P27/08 ,  H02P29/024

Abstract: A system in package encloses a sensor and motor driver circuit. In an implementation, the sensor is an integrated circuit micro-electro-mechanical-systems (MEMS) sensor and the driver circuit is a motor driver circuit. Non-motor winding data information is sensed by the MEMS sensor and processed for the purpose of characterizing known fault patterns for motors; characterizing normal operation of the motor; and evaluating continued operation of the motor to detect abnormal motor behavior and instances of motor fault. The motor is driven using PWM control and the information output by the MEMS sensor is sampled at sampling times having a fixed timing relationship relative to the PWM control signals.

公开(公告)号：US20180166469A1

公开(公告)日：2018-06-14

申请号：US15890910

申请日：2018-02-07

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L27/12 ,  H01L21/285 ,  H01L21/768 ,  H01L29/66 ,  H01L21/84 ,  H01L29/417

CPC classification number: H01L27/1211 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/845 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

Abstract: A transistor includes an active region supported by a substrate and having a source region, a channel region and a drain region. A gate stack extends over the channel region and a first sidewall surrounds the gate stack. A raised source region and a raised drain region are provided over the source and drain regions, respectively, of the active region adjacent the first sidewall. A second sidewall peripherally surrounds each of the raised source region and raised drain region. The second sidewall extends above a top surface of the raised source region and raised drain region to define regions laterally delimited by the first and second sidewalls. A conductive material fills the regions to form a source contact and a drain contact to the raised source region and raised drain region, respectively.

公开(公告)号：US09997463B2

公开(公告)日：2018-06-12

申请号：US15191359

申请日：2016-06-23

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L27/115 ,  H01L29/06 ,  H01L29/423 ,  H01L27/06 ,  H01L29/08 ,  H01L27/07 ,  H01L27/02 ,  H01L29/786 ,  H01L29/66 ,  H01L29/788 ,  H01L23/538 ,  H01L29/417 ,  H01L29/775 ,  H01L29/792 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11582 ,  H01L29/51

CPC classification number: H01L23/5386 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/5384 ,  H01L27/0255 ,  H01L27/0688 ,  H01L27/0705 ,  H01L27/0727 ,  H01L27/092 ,  H01L27/11582 ,  H01L29/0676 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/7926

Abstract: A modular interconnect structure facilitates building complex, yet compact, integrated circuits from vertical GAA FETs. The modular interconnect structure includes annular metal contacts to the transistor terminals, sectors of stacked discs extending radially outward from the vertical nanowires, and vias in the form of rods. Extension tabs mounted onto the radial sector interconnects permit signals to fan out from each transistor terminal. Adjacent interconnects are linked by linear segments. Unlike conventional integrated circuits, the modular interconnects as described herein are formed at the same time as the transistors. Vertical GAA NAND and NOR gates provide building blocks for creating all types of logic gates to carry out any desired Boolean logic function. Stacked vertical GAA FETs are made possible by the modular interconnect structure. The modular interconnect structure permits a variety of specialized vertical GAA devices to be integrated on a silicon substrate using standard CMOS processes.

公开(公告)号：US09991996B2

公开(公告)日：2018-06-05

申请号：US15006191

申请日：2016-01-26

Applicant: STMicroelectronics, Inc.

Inventor： Liwen Chu ,  George A. Vlantis

IPC: H04L5/00 ,  H04L1/16 ,  H04W72/12 ,  H04W72/04 ,  H04W74/08 ,  H04W84/12

CPC classification number: H04L5/003 ,  H04L1/16 ,  H04L1/1607 ,  H04L1/1854 ,  H04L5/0007 ,  H04L5/0037 ,  H04W72/04 ,  H04W72/121 ,  H04W72/1289 ,  H04W74/0816 ,  H04W84/12

Abstract: An access point (AP) contends for a medium during a contention period in order to obtain exclusive control of the medium for a certain time period that may include one or more transmission opportunities. The AP and client stations (STAs) communicate during the time period using orthogonal frequency division multiple access (OFDMA) techniques with scheduled use (i.e., allocation) of sub-channels of the medium. The AP controls this scheduling for down-link and up-link communications by sending control signaling to inform the STAs of the resource allocation schedule which specifies STAs involved in the OFDMA communications along with the sub-channel identification bandwidth allocated to each STA. The control signaling may be a combination of physical layer (PHY) and medium access control layer (MAC) communicated information.

公开(公告)号：US09983353B2

公开(公告)日：2018-05-29

申请号：US14933095

申请日：2015-11-05

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu

IPC: G02B6/10 ,  G02B6/136 ,  G02B6/122 ,  C30B29/06 ,  C30B23/04 ,  C30B25/04 ,  G02B6/13 ,  G02B6/12 ,  G02B6/032

CPC classification number: G02B6/107 ,  C30B23/04 ,  C30B25/04 ,  C30B29/06 ,  G02B6/032 ,  G02B6/122 ,  G02B6/131 ,  G02B6/136 ,  G02B2006/12061 ,  G02B2006/12173 ,  G02B2006/12176

Abstract: A strip of sacrificial semiconductor material is formed on top of a non-sacrificial semiconductor material substrate layer. A conformal layer of the non-sacrificial semiconductor material is epitaxially grown to cover the substrate layer and the strip of sacrificial semiconductor material. An etch is performed to selectively remove the strip of sacrificial semiconductor material and leave a hollow channel surrounded by the conformal layer and the substrate layer. Using an anneal, the conformal layer and the substrate layer are reflowed to produce an optical waveguide structure including the hollow channel.

公开(公告)号：US20180138898A1

公开(公告)日：2018-05-17

申请号：US15351542

申请日：2016-11-15

Applicant: STMicroelectronics, Inc.

Inventor： Pavan Nallamothu

IPC: H03K3/012 ,  H03K17/687 ,  G05F1/575

CPC classification number: H03K3/012 ,  G05F1/575 ,  H03K17/687

Abstract: A voltage generator circuit uses a feedback loop to regulate an output voltage at an output node. A pair of opposite conductivity source-follower transistors are coupled to the output node. A first one of the source-follower transistors operates to provide a fast current transient for charging a capacitive load that is switchably connected to the output node. A second one of the source-follower transistor operate under feedback control to regulate the voltage level at the output node.

公开(公告)号：US20180130623A1

公开(公告)日：2018-05-10

申请号：US15866552

申请日：2018-01-10

Applicant: STMicroelectronics, Inc.

Inventor： Thomas L. Hopkins

IPC: H01H35/02 ,  H01H35/14 ,  D06F75/26 ,  G05B9/02

CPC classification number: H01H35/02 ,  D06F75/26 ,  G05B9/02 ,  H01H35/14 ,  H01H2231/012

Abstract: A protective circuit for an apparatus includes an accelerometer having an output and a microcontroller coupled to the output of the accelerometer. The protective circuit also includes a switch for controlling the apparatus coupled to an output of the microcontroller and a load coupled to the switch. A power source is coupled to the load and the switch. In operation the microcontroller is cable of sending a signal to the switch to turn of power to the load when a dangerous condition as detected from the accelerometer data has occurred.

公开(公告)号：US09964777B2

公开(公告)日：2018-05-08

申请号：US14976937

申请日：2015-12-21

Applicant: STMicroelectronics, Inc.

Inventor： Mark A. Lysinger ,  Chih-Hung Tai ,  James L. Worley ,  Pavan Nallamothu

IPC: G02B27/64 ,  H02K41/035 ,  H02P7/025

CPC classification number: G02B27/646 ,  H02K41/0356 ,  H02P7/025

Abstract: Various embodiments provide an optical image stabilization circuit including a drive circuit having a power waveform generator and a power waveform conversion circuit. The power waveform generator generates a power waveform. The power waveform conversion circuit converts the power waveform to a power drive signal. An actuator is then driven by the power drive signal to move a lens accordingly and compensate for any movements and vibrations of a housing of the lens.

公开(公告)号：US09929253B2

公开(公告)日：2018-03-27

申请号：US15178853

申请日：2016-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.