公开(公告)号：US20240219633A1

公开(公告)日：2024-07-04

申请号：US18090258

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Brandon Marin ,  Jeremy Ecton ,  Gang Duan ,  Srinivas Pietambaram

IPC: G02B6/122 ,  G02B6/138

CPC classification number: G02B6/1221 ,  G02B6/138 ,  G02B2006/12038

Abstract: An integrated circuit (IC) module includes a photonic IC, an electrical IC, and a switchable waveguide device that, using a signal from the electrical IC, controls optical signals to or from the photonic IC. The switchable waveguide device may be formed by coupling metallization structures on both sides of, and either level with or below, a nonlinear optical material. The metallization structures may be in the photonic or electrical IC. The nonlinear optical material may be above the electrical IC in the photonic IC or on a glass substrate. The photonic and electrical ICs may be hybrid bonded or soldered together. The IC module may be coupled to a system substrate.

公开(公告)号：US20240219632A1

公开(公告)日：2024-07-04

申请号：US18091535

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Umesh Prasad ,  Suddhasattwa Nad ,  Benjamin T. Duong ,  Yi Yang

IPC: G02B6/122 ,  G02B1/02 ,  G02B3/00

CPC classification number: G02B6/122 ,  G02B1/02 ,  G02B3/0087 ,  G02B2006/12061

Abstract: Technologies for integrated graded index (GRIN) lenses for photonic circuits is disclosed. In one illustrative embodiment, a glass substrate has a cavity in which a GRIN lens is disposed. In other embodiments, the GRIN lens may be on a surface of the glass substrate. The GRIN lens focuses and collimates light to a free-space beam from a waveguide defined in the glass substrate. Another component such as a photonic integrated circuit (PIC) die may also have a GRIN lens and focus the free-space beam into a waveguide in the PIC die. The use of GRIN lenses allows for passive coupling to waveguides without further active alignment that minimizes signal transmission losses.

公开(公告)号：US20240217216A1

公开(公告)日：2024-07-04

申请号：US18091028

申请日：2022-12-29

Applicant: INTEL CORPORATION

Inventor： Kristof DARMAWIKARTA ,  Tarek A. IBRAHIM ,  Srinivas V. PIETAMBARAM ,  Dilan SENEVIRATNE ,  Jieying KONG ,  Thomas HEATON ,  Whitney BRYKS ,  Vinith BEJUGAM ,  Junxin WANG ,  Gang DUAN

IPC: B32B17/10 ,  B32B7/12 ,  B32B17/02 ,  B65D85/48

CPC classification number: B32B17/10642 ,  B32B7/12 ,  B32B17/02 ,  B65D85/48 ,  B32B2260/04 ,  B32B2307/202 ,  B32B2457/00

Abstract: Embodiments disclosed herein include package substrates with glass stiffeners. In an embodiment, the package substrate comprises a first layer, where the first layer comprises glass. In an embodiment, the package substrate comprises a second layer over the first layer, where the second layer is a buildup film. In an embodiment, the package substrate further comprises an electrically conductive interconnect structure through the first layer and the second layer.

公开(公告)号：US12028859B2

公开(公告)日：2024-07-02

申请号：US17314200

申请日：2021-05-07

Applicant: Intel Corporation

Inventor： Gang Xiong ,  Sergey Sosnin ,  Jie Zhu ,  Gregory Ermolaev

IPC: H04L5/00 ,  H04B7/06 ,  H04L1/1867 ,  H04W72/1268 ,  H04W72/21 ,  H04W72/23

CPC classification number: H04W72/21 ,  H04B7/0639 ,  H04L1/1887 ,  H04W72/1268 ,  H04W72/23

Abstract: A user equipment (UE) configured for physical uplink shared channel (PUSCH) repetition in an fifth-generation (5G) new radio (NR) network decodes a downlink control information (DCI) format that includes a scheduling grant for a PUSCH transmission. For a codebook-based PUSCH transmission, the DCI format indicates at least a first and a second transmit precoder matrix indicator (TPMI) index for PUSCH repetition. The UE may apply a precoder matrix determined from the first TPMI index to encode a PUSCH for a first PUSCH transmission occasion of the PUSCH repetition and may apply a precoder matrix determined from the second TPMI index to encode the PUSCH for a second PUSCH transmission occasion. For a non-codebook-based PUSCH transmission, the DCI format indicates at least a first and a second sounding reference signal (SRS) resource indicator (SRI) for PUSCH repetition. The UE may apply the first SRI to encode the PUSCH for the first PUSCH transmission occasion and may apply the second SRI to encode the PUSCH for the second PUSCH transmission occasion.

公开(公告)号：US12028443B2

公开(公告)日：2024-07-02

申请号：US16650439

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Eduardo Cabre ,  Nathan Heldt-Sheller ,  Ned M. Smith

IPC: H04L9/08 ,  G06F21/57

CPC classification number: H04L9/0825 ,  G06F21/575 ,  H04L9/0838 ,  H04L9/0866

Abstract: Various systems and methods for establishing security profiles for Internet of Things (IoT) devices and trusted platforms, including in OCF specification device deployments, are discussed herein. In an example, a technique for onboarding a subject device for use with a security profile, includes: receiving a request to perform an owner transfer method of a device associated with a device platform; verifying attestation evidence associated with the subject device, the attestation evidence being signed by a certificate produced using a manufacturer-embedded key, with the key provided from a trusted hardware component of the device platform; and performing device provisioning of the subject device, based on the attestation evidence, as the device provisioning causes the subject device to use a security profile tied to manufacturer-embedded keys.

公开(公告)号：US12028194B2

公开(公告)日：2024-07-02

申请号：US17753089

申请日：2020-09-28

Applicant: Intel Corporation

Inventor： Rainer Strobel ,  Ravindra Singh

IPC: H04L25/06 ,  H03M13/11 ,  H03M13/41 ,  H04L25/03

CPC classification number: H04L25/067 ,  H03M13/1125 ,  H03M13/4146 ,  H04L25/03038 ,  H04L25/03286

Abstract: A receiver for a passive optical network is provided. The receiver includes an analog-to-digital converter circuitry configured generate a digital receive signal based on an analog receive signal. The analog receive signal is based on an optical receive signal encoded with a binary transmit sequence. The receiver additionally comprises linear equalizer circuitry configured to generate an equalized receive signal by linearly equalizing the digital receive signal. Further, the receiver comprises secondary equalizer circuitry configured to generate soft information indicating a respective reliability of elements in the equalized receive signal using the Viterbi algorithm. In addition, the receiver comprises decoder circuitry configured to generate a digital output signal based on the soft information using soft decision forward error correction.

公开(公告)号：US12027458B2

公开(公告)日：2024-07-02

申请号：US17841551

申请日：2022-06-15

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/32139 ,  H01L21/76819 ,  H01L21/7682 ,  H01L21/76843 ,  H01L23/5283 ,  H01L23/53209

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

公开(公告)号：US12027417B2

公开(公告)日：2024-07-02

申请号：US16913320

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Suresh Vishwanath ,  Yulia Tolstova ,  Pratik Patel ,  Szuya S. Liao ,  Anand S. Murthy

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3215 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/76834 ,  H01L21/02532 ,  H01L21/28255 ,  H01L21/3215 ,  H01L21/76831 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66628

Abstract: Integrated circuit structures having source or drain structures with a high germanium concentration capping layer are described. In an example, an integrated circuit structure includes source or drain structures including an epitaxial structure embedded in a fin at a side of a gate stack. The epitaxial structure has a lower semiconductor layer and a capping semiconductor layer on the lower semiconductor layer with an abrupt interface between the capping semiconductor layer and the lower semiconductor layer. The lower semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of less than 40% at the abrupt interface. The capping semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of greater than 50% at the abrupt interface and throughout the capping semiconductor layer.

公开(公告)号：US12026304B2

公开(公告)日：2024-07-02

申请号：US17434603

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Kathy Bui ,  Paul Diefenbaugh ,  Kristoffer Fleming ,  Michael Rosenzweig ,  Soethiha Soe ,  Vishal Sinha ,  Nicholas Klein ,  Guangxin Xu ,  Stephan Jourdan

IPC: G09G5/00 ,  G06F1/3231 ,  G06F1/3234 ,  G06F1/3287 ,  G06F3/01 ,  G06N20/00 ,  G06V40/16 ,  G09G3/20 ,  G09G3/34 ,  H04M1/22

CPC classification number: G06F3/013 ,  G06F1/3231 ,  G06F1/3265 ,  G06F1/3287 ,  G06N20/00 ,  G06V40/166 ,  G06V40/171 ,  G09G3/2092 ,  G09G3/3406 ,  G09G2354/00 ,  G09G2360/144 ,  H04M1/22

Abstract: Example smart panel display apparatus and related methods are disclosed herein. An example apparatus to control a display of an electronic device includes a user presence detector to determine a presence of a user relative to the device based on image data generated by an image sensor of the device. The example apparatus includes a gaze detector to determine a direction of a gaze of the user relative to the image sensor based on the image data. The example apparatus includes a backlight manager to selectively adjust a display brightness based on the presence of the user and the direction of the gaze of the user.

公开(公告)号：US12026106B2

公开(公告)日：2024-07-02

申请号：US17802117

申请日：2020-03-30

Applicant: INTEL CORPORATION

Inventor： Keqiang Wu ,  Zhidong Yu ,  Cheng Xu ,  Samuel Ortiz ,  Weiting Chen

IPC: G06F13/38 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1678 ,  G06F13/1621 ,  G06F13/4004

Abstract: The present disclosure provides an interconnect for a non-uniform memory architecture platform to provide remote access where data can dynamically and adaptively be compressed and decompressed at the interconnect link. A requesting interconnect link can add a delay to before transmitting requested data onto an interconnect bus, compress the data before transmission, or packetize and compress data before transmission. Likewise, a remote interconnect link can decompress request data.