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    Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric
    64.
    发明授权
    Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric 失效
    用于同时形成沟槽电容器电介质和沟槽侧壁器件电介质的半导体方法和结构

    公开(公告)号：US06936512B2

    公开(公告)日：2005-08-30

    申请号：US10260085

    申请日：2002-09-27

    申请人： Michael P. Chudzik ,  Rajarao Jammy ,  Carl John Radens ,  Kenneth T. Settlemyer, Jr. ,  Padraic Shafer ,  Joseph F. Shepard, Jr.

    发明人： Michael P. Chudzik ,  Rajarao Jammy ,  Carl John Radens ,  Kenneth T. Settlemyer, Jr. ,  Padraic Shafer ,  Joseph F. Shepard, Jr.

    IPC分类号： H01L21/314 ,  H01L21/316 ,  H01L21/8242

    CPC分类号： H01L29/66181 ,  H01L21/3144 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/10864 ,  H01L27/10867

    摘要： Disclosed herein is a method, in an integrated, of forming a high-K node dielectric of a trench capacitor and a trench sidewall device dielectric at the same time. The method includes forming a trench in a single crystal layer of a semiconductor substrate, and forming an isolation collar along a portion of the trench sidewall, wherein the collar has a top below the top of the trench in the single crystal layer. Then, at the same time, a high-K dielectric is formed along the trench sidewall, the high-K dielectric extending in both an upper portion of the trench including above the isolation collar and in a lower portion of the trench below the isolation collar. The top of the isolation collar is then etched back to expose a portion of the single crystal substrate along the sidewall, and then, a node electrode is formed in conductive contact with the exposed sidewall and also in contact with the high-K dielectric in the lower portion, such that the high-K dielectric remains as a trench sidewall dielectric in the upper portion of the sidewall. In a DRAM memory cell structure, the trench sidewall dielectric may then be used as a gate dielectric of a vertical transistor which accesses the trench storage capacitor in the trench.

    摘要翻译： 本文公开了一种在同时形成沟槽电容器和沟槽侧壁装置电介质的高K节点电介质的集成方法。 所述方法包括在半导体衬底的单晶层中形成沟槽，以及沿着沟槽侧壁的一部分形成隔离环，其中所述环在所述单晶层中具有位于所述沟槽顶部下方的顶部。 然后，同时，沿着沟槽侧壁形成高K电介质，高K电介质在包括隔离环的上方的沟槽的上部和隔离环的下方的沟槽的下部延伸 。 然后隔离环的顶部被回蚀以沿着侧壁露出单晶衬底的一部分，然后，形成与暴露的侧壁导电接触并且还与高K电介质接触的节点电极 使得高K电介质保留在侧壁的上部中的沟槽侧壁电介质。 在DRAM存储单元结构中，沟槽侧壁电介质可以用作访问沟槽中的沟槽存储电容器的垂直晶体管的栅极电介质。

    Formation of self-aligned buried strap connector
    69.
    发明授权
    Formation of self-aligned buried strap connector 失效
    自对准埋地连接器的形成

    公开(公告)号：US06579759B1

    公开(公告)日：2003-06-17

    申请号：US10227396

    申请日：2002-08-23

    申请人： Michael Patrick Chudzik ,  Jochen Beintner ,  Ramachandra Divakaruni ,  Rajarao Jammy

    发明人： Michael Patrick Chudzik ,  Jochen Beintner ,  Ramachandra Divakaruni ,  Rajarao Jammy

    IPC分类号： H01L218242

    CPC分类号： H01L27/10867 ,  H01L27/10841 ,  H01L29/66181

    摘要： In a vertical-transistor DRAM cell, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a temporary insulator layer, forming a vertical spacer on the trench walls above the temporary insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the DRAM cell.

    摘要翻译： 在垂直晶体管DRAM单元中，通过以下方式解决了深沟槽电容器的节点与垂直晶体管的下电极之间可靠的电连接的问题; 沉积临时绝缘体层，在临时绝缘体上方的沟槽壁上形成垂直间隔物，然后剥离绝缘体以露出衬底壁; 将掺杂剂扩散到衬底壁中以形成埋入带的自对准延伸部; 沉积最后的栅极绝缘体; 然后形成DRAM单元的上部。