公开(公告)号：US09842832B2

公开(公告)日：2017-12-12

申请号：US15183179

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  John S. Guzek ,  Johanna M. Swan ,  Christopher J. Nelson ,  Nitin A. Deshpande ,  William J. Lambert ,  Charles A. Gealer ,  Feras Eid ,  Islam A. Salama ,  Kemal Aygun ,  Sasha N. Oster ,  Tyler N. Osborn

IPC: H01L25/16 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H05K1/18

CPC classification number: H01L25/16 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/50 ,  H01L24/86 ,  H01L25/00 ,  H01L25/0655 ,  H01L2224/0405 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/29078 ,  H01L2224/86203 ,  H01L2224/86815 ,  H05K1/185 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.

公开(公告)号：US09520376B2

公开(公告)日：2016-12-13

申请号：US14875247

申请日：2015-10-05

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Deepak Kulkarni ,  Chia-Pin Chiu ,  Tannaz Harirchian ,  John S. Guzek

IPC: H01L23/28 ,  H01L23/00 ,  H01L23/367 ,  H01L23/433 ,  H01L23/498 ,  H01L23/538 ,  H01L23/36 ,  H01L21/56 ,  H01L23/34 ,  H01L25/18

CPC classification number: H01L24/20 ,  H01L21/56 ,  H01L23/34 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/211 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/00

Abstract: An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.

公开(公告)号：US09496211B2

公开(公告)日：2016-11-15

申请号：US13684110

申请日：2012-11-21

Applicant: INTEL CORPORATION

Inventor： Deepak V. Kulkarni ,  Russell K. Mortensen ,  John S. Guzek

IPC: H01L23/498 ,  H01L21/50 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L28/40 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2224/92224 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate including a plurality of build-up layers, such as bumpless build-up layer (BBUL). In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.

Abstract translation: 本公开的实施例涉及包装组件，以及用于形成包装组件和包含包装组件的系统的方法。 封装组件可以包括包括多个堆积层的衬底，例如无扰性积聚层（BBUL）。 在各种实施例中，电路由特征可以设置在衬底的外表面上。 在各种实施例中，主逻辑管芯和第二管芯或电容器可以嵌入在多个堆积层中。 在各种实施例中，可以在多个积层中定义电路径，以便绕过主逻辑管芯来路由第二管芯或电容器之间的电功率或接地信号与电路径特征。

公开(公告)号：US20160300824A1

公开(公告)日：2016-10-13

申请号：US15183179

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  John S. Guzek ,  Johanna M. Swan ,  Christopher J. Nelson ,  Nitin A. Deshpande ,  William J. Lambert ,  Charles A. Gealer ,  Feras Eid ,  Islam A. Salama ,  Kemal Aygun ,  Sasha N. Oster ,  Tyler N. Osborn

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/16 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/50 ,  H01L24/86 ,  H01L25/00 ,  H01L25/0655 ,  H01L2224/0405 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/29078 ,  H01L2224/86203 ,  H01L2224/86815 ,  H05K1/185 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.

公开(公告)号：US20160197065A1

公开(公告)日：2016-07-07

申请号：US15068262

申请日：2016-03-11

Applicant: Intel Corporation

Inventor： John S. Guzek ,  Debendra Mallik ,  Sasha N. Oster ,  Timothy E. McIntosh

IPC: H01L25/18 ,  H01L23/367 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/2518 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15321 ,  H01L2924/16251 ,  H01L2924/182

Abstract: Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed.

公开(公告)号：US20160190027A1

公开(公告)日：2016-06-30

申请号：US15065533

申请日：2016-03-09

Applicant: Intel Corporation

Inventor： Rahul N. Manepalli ,  Hamid R. Azimi ,  John S. Guzek

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/50 ,  H01L23/00 ,  H01L23/528

CPC classification number: H01L23/3121 ,  H01L21/561 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/50 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/96 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/3511 ,  H05K3/0097 ,  H05K3/4679 ,  H05K3/4682 ,  H05K2201/09918 ,  H05K2203/1536 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: Methods of forming molded panel coreless package structures are described. Those methods and structures may include fabrication of embedded die packages using large panel format and use of molding to improve rigidity of the panel, as well as to embed the die in a non-sacrificial mold material. The methods and structures described include methods for manufacturing thin, coreless substrate architectures which possess low warpage.

Abstract translation: 描述形成模制板无芯封装结构的方法。 这些方法和结构可以包括使用大面板格式制造嵌入式模具封装并使用模制来提高面板的刚度，以及将模具嵌入非牺牲模具材料中。 所描述的方法和结构包括制造具有低翘曲的薄的无芯基板结构的方法。

公开(公告)号：US09287248B2

公开(公告)日：2016-03-15

申请号：US14104877

申请日：2013-12-12

Applicant: INTEL CORPORATION

Inventor： John S. Guzek ,  Debendra Mallik ,  Sasha N. Oster ,  Timothy E. McIntosh

IPC: H01L23/52 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/2518 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15321 ,  H01L2924/16251 ,  H01L2924/182

Abstract: Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了允许诸如处理器和存储器的设备之间的相对短的连接的集成电路封装组件。 在一个实施例中，封装组件包括嵌入到直接耦合到附接到子封装的另一管芯的子封装中的管芯。 在一些实施例中，子包还可以包含电源管理装置。 在一些实施例中，嵌入在子封装和/或功率管理器件中的管芯可以与耦合到子封装的管芯定义的区域重叠或位于其中，使得它们位于耦合到子封装的管芯和衬底之间 子包。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20150145138A1

公开(公告)日：2015-05-28

申请号：US14614687

申请日：2015-02-05

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  John S. Guzek

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/3105 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L21/4853 ,  H01L21/31053 ,  H01L21/50 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/522 ,  H01L23/5389 ,  H01L23/64 ,  H01L24/16 ,  H01L24/19 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

Abstract translation: 重构的晶片包括具有平坦表面的刚性块和平行于平坦表面设置的基底表面。 多个骰子嵌入刚体中。 多个骰子包括通过与平坦表面共面露出的端子。 形成重构的晶片的过程包括去除刚性质量块中的一些以露出端子，同时将多个裸片保持在刚性质量块中。 形成设备的过程包括将一个设备与重构的晶片分开。

公开(公告)号：US20150104907A1

公开(公告)日：2015-04-16

申请号：US14570785

申请日：2014-12-15

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Deepak Kulkarni ,  Chia-Pin Chiu ,  Tannaz Harirchian ,  John S. Guzek

IPC: H01L23/00 ,  H01L23/34 ,  H01L21/56

CPC classification number: H01L24/20 ,  H01L21/56 ,  H01L23/34 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/211 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/00

Abstract: An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.

Abstract translation: 一个实例包括包括具有下模表面的微电子管芯，平行于下模表面的上模表面和管芯侧的管芯封装，该微电子管芯包括有源区和非活性区。 该实施例可选地包括具有较低散热器表面的散热器，平行于下部散热器表面的上部散热器表面和至少一个散热器侧，散热器布置在热电连接的微电子管芯的上表面上 具有裸片的非活性区域并与活性区电绝缘。 该实施例可选地包括封装模具侧和散热器侧和下部散热器表面的封装材料，该封装材料包括基本上平行于模具下表面的下表面和基本上平行于模具上表面的上表面。