公开(公告)号：US5897334A

公开(公告)日：1999-04-27

申请号：US951062

申请日：1997-10-15

申请人： Sun Ho Ha ,  Young Wook Heo ,  Byung Joon Han

发明人： Sun Ho Ha ,  Young Wook Heo ,  Byung Joon Han

IPC分类号： H01L23/28 ,  H01L21/50 ,  H01L21/66 ,  H01L23/12 ,  H01L23/498 ,  H05K1/00 ,  H05K3/00 ,  H05K3/22 ,  H01L21/44

CPC分类号： H01L22/22 ,  H01L23/4985 ,  H01L24/97 ,  H05K3/0097 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0393 ,  H05K2201/09063 ,  H05K2201/0909 ,  H05K2203/1545 ,  H05K3/0052 ,  H05K3/225

摘要： A method for reproducing a PCB strip for semiconductor packages, wherein a poor quality PCB unit included in the PCB strip is replaced with a normal quality one, thereby achieving a reduction in the amount of package materials used and an improvement in the process efficiency. The invention also provides a method for fabricating semiconductor packages using the PCB strip reproduction method. A desired portion of a poor quality PCB unit included in a PCB strip is cut out in such a manner that a cutting opening having a peripheral edge extending along the singulation line of the poor quality PCB unit or along a region defined between the singulation line and anti-bending slots of the poor quality PCB unit. In the cutting opening, a separate good quality PCB unit member having the same shape and size as the cutting opening is then fitted. Thus, it is possible to simply and efficiently replace PCB units determined to be of poor quality with separate good quality PCB unit members, respectively.

摘要翻译： 一种用于再现用于半导体封装的PCB板的方法，其中包括在PCB板中的劣质PCB单元被正常的质量替换，从而实现所使用的封装材料的量的减少和工艺效率的提高。 本发明还提供了一种使用PCB条带再现方法制造半导体封装的方法。 包含在PCB带中的劣质PCB单元的期望部分以这样的方式被切出：具有周边边缘的切割开口沿着劣质PCB单元的单线延伸，或者沿着限定在单线线和 抗弯槽的质量差的PCB单元。 在切割开口中，然后安装具有与切割开口相同的形状和尺寸的单独的优质PCB单元构件。 因此，可以分别用单独的优质PCB单元构件简单有效地替代被确定为质量差的PCB单元。

公开(公告)号：US5834160A

公开(公告)日：1998-11-10

申请号：US586347

申请日：1996-01-16

申请人： Alan E. Ferry ,  Byung Joon Han ,  Maureen Yee Lau ,  Robert T. Scruton, Sr. ,  King Lien Tai

发明人： Alan E. Ferry ,  Byung Joon Han ,  Maureen Yee Lau ,  Robert T. Scruton, Sr. ,  King Lien Tai

IPC分类号： G03F7/20 ,  H05K3/00 ,  H05K3/06 ,  G03C5/00 ,  G03B27/52

CPC分类号： G03F7/70216 ,  G03F7/2002 ,  G03F7/70241 ,  G03F7/70791 ,  H05K3/0082

摘要： The present inventors have discovered that fine patterns of metal or insulator can be formed on printed circuit board using conventional lithographic steppers with inverted projection lenses. The inverted projection lenses act as enlargement lenses rather than reducing lenses and exhibit a large depth of focus sufficient to accommodate the deviations of PC board from planarity. The inverted lens reduces the size of the image needed at the mask, permitting multiple mask levels to be combined on a single glass. This reduces the cost of the mask set and permits the use of smaller glass masks having greater accuracy and dimensional stability than the convention mylar masks used for PC board. By inverting the projection lenses on near-obsolete steppers, applicants were able to form metal patterns on PC board of finer dimension than heretofore reported. Inverting a 5.times. ZEISS lens on a GCA 6300A stepper, applicants were able to form vias of less than 25 .mu.m diameter, pattern metal lines and spaces of less than 25 .mu.m, and obtain overlay registration accuracy of less than 25 .mu.m. The field size was larger than 1 in.sup.2, and the depth of focus was greater than 50 .mu.m.

摘要翻译： 本发明人已经发现，使用具有倒置投影透镜的常规光刻步进器可以在印刷电路板上形成金属或绝缘体的精细图案。 反转的投影透镜作为放大透镜而不是减少透镜并且展现出足够的焦深以适应PC板与平面度的偏差。 倒置的镜头减少了掩模所需的图像的尺寸，允许在单个玻璃上组合多个掩模级别。 这降低了掩模组的成本，并且允许使用比用于PC板的常规聚酯薄膜掩模更大的精度和尺寸稳定性的较小的玻璃面罩。 通过将投影镜片倒置在近陈旧的步进器上，申请人能够在PC板上形成比迄今报告的更细的尺寸的金属图案。 将5x蔡司镜头倒置在GCA 6300A步进机上，申请人能够形成直径小于25微米的通孔，图案金属线和小于25微米的间隙，并获得小于25微米的覆盖对准精度。 场尺寸大于1 in2，焦点深度大于50m。

公开(公告)号：US5646828A

公开(公告)日：1997-07-08

申请号：US697121

申请日：1996-08-20

申请人： Yinon Degani ,  Thomas Dixon Dudderar ,  Byung Joon Han ,  Alan Michael Lyons

发明人： Yinon Degani ,  Thomas Dixon Dudderar ,  Byung Joon Han ,  Alan Michael Lyons

IPC分类号： H01L25/18 ,  H01L23/13 ,  H01L23/14 ,  H01L23/24 ,  H01L23/367 ,  H01L23/538 ,  H01L25/04 ,  H01L25/065 ,  H01L25/07 ,  H01L25/16 ,  H05K1/14 ,  H05K1/18 ,  H05K7/20

CPC分类号： H01L25/162 ,  H01L23/13 ,  H01L23/147 ,  H01L23/24 ,  H01L23/3677 ,  H01L23/5385 ,  H01L25/0655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/3025 ,  H05K1/141 ,  H05K1/142 ,  H05K1/182

摘要： A novel packaging of semiconductor elements, such as MCM tiles, with a variety of printed circuit or wired boards (PWB), the packages occupying a small size, at least in the vertical direction, relative to prior art OMPAC devices. The MCM tile includes an interconnection substrate with peripheral metallizations and at least one chip or integrated circuit (IC) mounted on the substrate by solder reflow or conductive adhesive technology. The PWB which may be a single level or a multilevel, is provided with an aperture for accommodation of at least one chip therein. Depending on the type of interconnection between the substrate and the PWB, the aperture may be larger than the substrate of the MCM tile for wire bonding interconnection or smaller than the substrate for solder reflow or conductive adhesive interconnection. In the wire bonding case, the MCM tile is positioned within the aperture resting on the surface of the PWB or of a structural member or of a heat sink which encloses one end of the aperture. The other end of the aperture may be open or enclosed by a structural member, a heat sink, another PWB or a mother board. For solder reflow or conductive adhesive interconnection, the substrate which is larger than the aperture is positioned so that its ends overlap areas of the PWB adjacent the aperture and the chips and/or substrate are positioned within the aperture. The interconnections are enclosed in a compliable encapsulating material, such as silica gel.

摘要翻译： 相对于现有技术的OMPAC设备，至少在垂直方向上具有小尺寸的半导体元件（例如MCM瓦片）与各种印刷电路板或布线板（PWB）的新型封装。 MCM瓦片包括具有外围金属化的互连基板和通过焊料回流或导电粘合技术安装在基板上的至少一个芯片或集成电路（IC）。 可以是单级或多级的PWB设置有用于在其中容纳至少一个芯片的孔。 根据基板和PWB之间的互连类型，孔径可能大于用于引线接合互连的MCM瓦片的基板，或者小于用于焊料回流或导电粘合剂互连的基板。 在引线接合壳体中，MCM瓦片位于留在PWB的表面上的孔内，或者围绕孔的一端的结构构件或散热器。 孔的另一端可以由结构构件，散热器，另一PWB或母板打开或封闭。 对于焊料回流或导电粘合剂互连，大于孔的衬底被定位成使得其端部与邻近孔的重叠区域重叠，并且芯片和/或衬底位于孔内。 互连被封装在可复制的封装材料中，例如硅胶。

公开(公告)号：US20120146192A1

公开(公告)日：2012-06-14

申请号：US12967223

申请日：2010-12-14

申请人： Byung Joon Han ,  Byung Tai Do ,  Arnel Senosa Trasporto ,  Henry Descalzo Bathan

发明人： Byung Joon Han ,  Byung Tai Do ,  Arnel Senosa Trasporto ,  Henry Descalzo Bathan

IPC分类号： H01L29/06 ,  H01L21/52

CPC分类号： H01L23/49503 ,  H01L23/49513 ,  H01L23/49582 ,  H01L24/32 ,  H01L2224/27013 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/14 ,  H01L2924/00

摘要： A method of manufacture of an integrated circuit mounting system includes: providing a die paddle with a component side having a die mount area and a recess with more than one geometric shape; applying an adhesive on the die mount area and in a portion of the recess; and mounting an integrated circuit device with an inactive side directly on the adhesive.

摘要翻译： 一种制造集成电路安装系统的方法包括：提供具有模具安装区域的组件侧的模板和具有多于几何形状的凹部; 在模具安装区域和凹部的一部分中施加粘合剂; 并将具有非活性侧的集成电路装置直接安装在粘合剂上。

公开(公告)号：US07880293B2

公开(公告)日：2011-02-01

申请号：US12055171

申请日：2008-03-25

申请人： Byung Joon Han ,  Nathapong Suthiwongsunthorn ,  Pandi Chelvam Marimuthu ,  Kock Liang Heng

发明人： Byung Joon Han ,  Nathapong Suthiwongsunthorn ,  Pandi Chelvam Marimuthu ,  Kock Liang Heng

IPC分类号： H01L23/04

CPC分类号： H01L23/147 ,  H01L21/563 ,  H01L23/49822 ,  H01L23/552 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2224/05599

摘要： A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer exposing the conductive layer, a second via formed in the carrier wafer exposing the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second passivation layers are deposited over the first and second metal layers. The first or second passivation layer has an etched portion to expose a portion of the first metal layer or second metal layer.

摘要翻译： 半导体器件具有用于支撑器件的晶片和形成在晶片顶表面上的导电层。 载体晶片永久地接合在导电层上。 在晶片和载体晶片内形成互连结构。 所述互连结构包括形成在所述晶片中的暴露所述导电层的第一通孔，暴露所述导电层的所述载体晶片中形成的第二通孔，沉积在所述第一通孔上的第一金属层，所述第一金属层与所述导电层电接触 以及沉积在所述第二通孔上的第二金属层，所述第二金属层与所述导电层电接触。 第一和第二钝化层沉积在第一和第二金属层上。 第一钝化层或第二钝化层具有蚀刻部分以暴露第一金属层或第二金属层的一部分。

公开(公告)号：US07525812B2

公开(公告)日：2009-04-28

申请号：US11877613

申请日：2007-10-23

申请人： Dean Paul Kossives ,  Byung Joon Han

发明人： Dean Paul Kossives ,  Byung Joon Han

IPC分类号： H05K7/00

CPC分类号： H05K1/16 ,  H01L23/3677 ,  H01L23/645 ,  H01L23/66 ,  H01L25/16 ,  H01L2223/6622 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/0237 ,  H05K1/141 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/0191 ,  H05K2201/10674 ,  Y10T29/49124 ,  Y10T29/49155 ,  H01L2224/05599

摘要： A substrate having a ground plane, a first side, and a second side is provided. A via that electrically connects the first side to the second side is formed. A printed wire is formed on the first side, and a printed wire is formed on the second side. A passive component is formed on the first side. The passive component is formed free of the ground plane. An active component is attached to the first side.

摘要翻译： 提供具有接地面，第一面和第二面的基板。 形成将第一侧电连接到第二侧的通孔。 印刷线形成在第一侧上，印刷线形成在第二面上。 在第一侧形成无源部件。 无源部件形成为没有接地平面。 活动部件附接到第一侧。

公开(公告)号：US07413933B2

公开(公告)日：2008-08-19

申请号：US11697779

申请日：2007-04-09

申请人： Jeffrey D. Punzalan ,  Jae Hun Ku ,  Byung Joon Han

发明人： Jeffrey D. Punzalan ,  Jae Hun Ku ,  Byung Joon Han

IPC分类号： H01L21/44

CPC分类号： H01L23/49503 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor including a leadframe having a die attach paddle and a number of leads is provided. The die attach paddle has a recess to provide a number of mold dams around the periphery of the die attach paddle. An integrated circuit is positioned in the recess. Electrical connections between the integrated circuit and the number of leads are made, and an encapsulant is formed over the integrated circuit and around the number of mold dams.

摘要翻译： 提供了包括具有管芯附接焊盘和多个引线的引线框的半导体。 管芯附接板具有凹部以在管芯附接板的周边周围提供多个模具坝。 集成电路位于凹槽中。 在集成电路和引线数之间进行电连接，并且在集成电路上形成密封剂并且围绕模具坝的数量。

公开(公告)号：US07135760B2

公开(公告)日：2006-11-14

申请号：US10446275

申请日：2003-05-23

申请人： Byung Joon Han ,  Byung Hoon Ahn

发明人： Byung Joon Han ,  Byung Hoon Ahn

IPC分类号： H01L23/495

CPC分类号： H01L24/32 ,  H01L23/49503 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A leadframe for a semiconductor die includes signal leads, ground leads, and a die support holder for supporting the semiconductor die. The die support holder has opposite surfaces and side edges therebetween. The opposite die support holder surfaces are smaller in transverse extent than the semiconductor die for supporting the die on one of the opposite die support holder surfaces such that the die extends beyond the side edges of the die support holder.

摘要翻译： 用于半导体管芯的引线框架包括信号引线，接地引线和用于支撑半导体管芯的管芯支撑保持器。 模具支撑架具有相对的表面和侧边。 相对的模具支撑保持器表面的横向范围比用于在相对的模具支撑保持器表面中的一个上支撑模具的半导体模具更小，使得模具延伸超过模具支撑保持器的侧边缘。

公开(公告)号：US06630373B2

公开(公告)日：2003-10-07

申请号：US10083993

申请日：2002-02-26

申请人： Jeffrey D. Punzalan ,  Hien Boon Tan ,  Zheng Zheng ,  Jae Hak Yee ,  Byung Joon Han

发明人： Jeffrey D. Punzalan ,  Hien Boon Tan ,  Zheng Zheng ,  Jae Hak Yee ,  Byung Joon Han

IPC分类号： H01L2144

CPC分类号： H01L23/49541 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A new design is provided for the design of a leadframe of a semiconductor package. A ground plane is added to the design of the leadframe, the ground frame is located between the leadframe and the die attach paddle over which the semiconductor device is mounted.

摘要翻译： 为半导体封装的引线框的设计提供了新的设计。 接地平面被添加到引线框架的设计中，接地框架位于引导框架和芯片附接板之间，半导体器件安装在其上。

公开(公告)号：US5977624A

公开(公告)日：1999-11-02

申请号：US8552

申请日：1998-01-16

申请人： Young Wook Heo ,  Byung Joon Han

发明人： Young Wook Heo ,  Byung Joon Han

IPC分类号： H01L23/31 ,  H01L23/053 ,  H01L23/12 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L23/3114 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311

摘要： A chip size semiconductor package with a light, thin, simple and compact structure having a reduced size of its semiconductor chip while having an increased number of pins and without degrading its functions. For the package, it is possible to use either the semiconductor chip having bond pads arranged on end portions of the chip or the semiconductor chip having bond pads arranged on the central portion of the chip. In either case, input/output terminals of the package are arranged in the form of an area array. Accordingly, when the package is mounted on an electronic appliance, its mounting area can be minimized, thereby achieving a compactness of the final product.

摘要翻译： 具有轻，薄，简单且紧凑结构的芯片尺寸半导体封装，其半导体芯片的尺寸减小，同时具有增加的引脚数量并且不降低其功能。 对于封装，可以使用具有布置在芯片的端部上的接合焊盘的半导体芯片或具有布置在芯片的中心部分上的接合焊盘的半导体芯片。 在任一情况下，封装的输入/输出端子以区域阵列的形式布置。 因此，当将包装安装在电子设备上时，其安装面积可以最小化，从而实现最终产品的紧凑性。