公开(公告)号：US20100081271A1

公开(公告)日：2010-04-01

申请号：US12242384

申请日：2008-09-30

申请人： Tadahiro Ishizaka ,  Shigeru Mizuno

发明人： Tadahiro Ishizaka ,  Shigeru Mizuno

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76873 ,  H01L23/53238

摘要： A method of forming an interconnect structure is provided. The method includes depositing a cobalt metal layer in an interconnect opening formed within a dielectric material containing a dielectric reactant element. The method further includes, in any order, thermally reacting at least a portion of the cobalt metal layer with at least a portion of the dielectric material to form a diffusion barrier containing a compound of the reactive metal from the cobalt metal layer and the dielectric reactant element from the dielectric material, and forming a cobalt nitride adhesion layer in the interconnect opening. The method further includes filling the interconnect opening with Cu metal, where the diffusion barrier and the cobalt nitride adhesion layer surround the Cu metal in the interconnect opening.

摘要翻译： 提供一种形成互连结构的方法。 该方法包括在形成在包含介电反应物元件的电介质材料内的互连开口中沉积钴金属层。 该方法还包括以任何顺序使钴金属层的至少一部分与电介质材料的至少一部分热反应形成包含来自钴金属层和介电反应物的反应性金属化合物的扩散阻挡层 元件，并且在互连开口中形成氮化钴粘合层。 该方法还包括用Cu金属填充互连开口，其中扩散阻挡层和氮化钴粘合层围绕互连开口中的Cu金属。

公开(公告)号：US20100046134A1

公开(公告)日：2010-02-25

申请号：US12588809

申请日：2009-10-28

申请人： Shigeru Mizuno ,  Masahito Ishihara ,  Sunil Wickramanayaka ,  Naoki Miyazaki

发明人： Shigeru Mizuno ,  Masahito Ishihara ,  Sunil Wickramanayaka ,  Naoki Miyazaki

IPC分类号： H01L21/683

CPC分类号： H01L21/6875 ,  H01L21/6833 ,  H02N13/00

摘要： An electrostatic chuck device provided with a dielectric plate with a surface embossed to give it a plurality of projections, an electrode, and an external power source, wherein substrate supporting surfaces of the plurality of projections are covered by conductor wiring and the conductor wiring electrically connects the substrate supporting surfaces of the plurality of projections. At the time of substrate processing, when the embossed projections contact the back of the substrate, the back of the substrate and the conductor wiring is made the same in potential due to the migration of the charges, the generation of force between the back of the substrate and the conductor wiring being in contact with the same is prevented, and a rubbing state between the two is prevented. Due to this, the electrostatic chuck device reduces the generation of particles, easily and stably removes and conveys substrates, and realizes a high yield and system operating rate.

公开(公告)号：US20100015798A1

公开(公告)日：2010-01-21

申请号：US12173814

申请日：2008-07-15

申请人： Kenji Suzuki ,  Frank M. Cerio, JR. ,  Miho Jomen ,  Shigeru Mizuno ,  Yasushi Mizusawa ,  Tadahiro Ishizaka

发明人： Kenji Suzuki ,  Frank M. Cerio, JR. ,  Miho Jomen ,  Shigeru Mizuno ,  Yasushi Mizusawa ,  Tadahiro Ishizaka

IPC分类号： H01L21/4763

CPC分类号： H01L21/76849 ,  C23C16/02 ,  C23C16/16 ,  H01L21/02068 ,  H01L21/28562 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76868 ,  H01L21/76883

摘要： A method for integrating ruthenium (Ru) metal cap layers and modified Ru metal cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration (EM) and stress migration (SM) in bulk Cu metal. In one embodiment, the method includes providing a planarized patterned substrate containing a Cu metal surface and a dielectric layer surface, depositing first Ru metal on the Cu metal surface, and depositing additional Ru metal on the dielectric layer surface, where the amount of the additional Ru metal is less than the amount of the first Ru metal. The method further includes at least substantially removing the additional Ru metal from the dielectric layer surface to improve the selective formation of a Ru metal cap layer on the Cu metal surface. Other embodiments further include incorporating one or more types of modifier elements into the dielectric layer surface, the Cu metal surface, the Ru metal cap layer, or a combination thereof.

摘要翻译： 将钌（Ru）金属盖层和改性的Ru金属覆盖层整合到半导体器件的铜（Cu）金属化中以改善块状Cu金属中的电迁移（EM）和应力迁移（SM）的方法。 在一个实施例中，该方法包括提供包含Cu金属表面和电介质层表面的平坦化图案化衬底，在Cu金属表面上沉积第一Ru金属，以及在电介质层表面上沉积额外的Ru金属，其中额外的量 Ru金属少于第一Ru金属的量。 该方法还包括从电介质层表面至少基本上去除额外的Ru金属，以改善在Cu金属表面上的Ru金属覆盖层的选择性形成。 其他实施例还包括将一种或多种类型的改性剂元素结合到电介质层表面，Cu金属表面，Ru金属覆盖层或其组合中。

公开(公告)号：US20080237859A1

公开(公告)日：2008-10-02

申请号：US11691167

申请日：2007-03-26

申请人： Tadahiro Ishizaka ,  Satohiko Hoshino ,  Kuzuhiro Hamamoto ,  Shigeru Mizuno ,  Yasushi Mizusawa

发明人： Tadahiro Ishizaka ,  Satohiko Hoshino ,  Kuzuhiro Hamamoto ,  Shigeru Mizuno ,  Yasushi Mizusawa

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure for an integrated circuit and method of forming the interconnect structure. The method includes depositing a metallic layer containing a reactive metal in an interconnect opening formed within a dielectric material containing a dielectric reactant element, thermally reacting at least a portion of the metallic layer with at least a portion of the dielectric material to form a diffusion barrier primarily containing a compound of the reactive metal from the metallic layer and the dielectric reactant element from the dielectric material, and filling the interconnect opening with Cu metal, where the diffusion barrier surrounds the Cu metal within the opening. The reactive metal can be Co, Ru, Mo, W, or Ir, or a combination thereof. The interconnect opening can be a trench, a via, or a dual damascene opening.

摘要翻译： 用于集成电路的互连结构和形成互连结构的方法。 该方法包括在包含介电反应物元件的电介质材料中形成的互连开口中沉积含有活性金属的金属层，使金属层的至少一部分与电介质材料的至少一部分热反应形成扩散阻挡层 主要包含来自金属层的反应性金属的化合物和来自电介质材料的介电反应物元件，并且用Cu金属填充互连开口，其中扩散阻挡层围绕开口内的Cu金属。 反应性金属可以是Co，Ru，Mo，W或Ir，或它们的组合。 互连开口可以是沟槽，通孔或双镶嵌开口。

公开(公告)号：US20060158823A1

公开(公告)日：2006-07-20

申请号：US11370893

申请日：2006-03-09

申请人： Shigeru Mizuno ,  Masahito Ishihara ,  Sunil Wickramanayaka ,  Naoki Miyazaki

发明人： Shigeru Mizuno ,  Masahito Ishihara ,  Sunil Wickramanayaka ,  Naoki Miyazaki

IPC分类号： H01L21/683

CPC分类号： H01L21/6875 ,  H01L21/6833 ,  H02N13/00

摘要： An electrostatic chuck device provided with a dielectric plate with a surface embossed to give it a plurality of projections, an electrode, and an external power source, wherein substrate supporting surfaces of the plurality of projections are covered by conductor wiring and the conductor wiring electrically connects the substrate supporting surfaces of the plurality of projections. At the time of substrate processing, when the embossed projections contact the back of the substrate, the back of the substrate and the conductor wiring is made the same in potential due to the migration of the charges, the generation of force between the back of the substrate and the conductor wiring being in contact with the same is prevented, and a rubbing state between the two is prevented. Due to this, the electrostatic chuck device reduces the generation of particles, easily and stably removes and conveys substrates, and realizes a high yield and system operating rate.

公开(公告)号：US06974721B2

公开(公告)日：2005-12-13

申请号：US10496690

申请日：2003-08-28

申请人： Naoyuki Koizumi ,  Kei Murayama ,  Shigeru Mizuno ,  Takashi Kurihara

发明人： Naoyuki Koizumi ,  Kei Murayama ,  Shigeru Mizuno ,  Takashi Kurihara

IPC分类号： H01L21/301 ,  H01L21/00 ,  H01L21/02 ,  H01L21/68 ,  H01L21/78 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/6835 ,  H01L21/67092 ,  H01L21/67132 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/27 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2224/274 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/3512 ,  H01L2924/00

摘要： In manufacturing a thin semiconductor chip, a wafer is stably held during processing to maintain a stable shape and to avoid generation of cracks on the wafer. When a thin wafer having a surface thereon is to be processed, a rigid support body is adhered to the other surface of the thin wafer and a ring-shaped frame, encircling an outer periphery of the thin wafer, is adhered to the rigid support body.

摘要翻译： 在制造薄的半导体芯片时，晶片在加工过程中被稳定地保持以保持稳定的形状并且避免在晶片上产生裂纹。 当要处理其上具有表面的薄晶片时，刚性支撑体粘附到薄晶片的另一个表面，并且围绕薄晶片的外周的环形框架被粘附到刚性支撑体 。

公开(公告)号：US20050176169A1

公开(公告)日：2005-08-11

申请号：US10496690

申请日：2003-08-28

申请人： Naoyuki Koizumi ,  Kei Murayama ,  Shigeru Mizuno ,  Takashi Kurihara

发明人： Naoyuki Koizumi ,  Kei Murayama ,  Shigeru Mizuno ,  Takashi Kurihara

IPC分类号： H01L21/301 ,  H01L21/00 ,  H01L21/02 ,  H01L21/68 ,  H01L21/78 ,  H01L21/44

CPC分类号： H01L21/6835 ,  H01L21/67092 ,  H01L21/67132 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/27 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2224/274 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/3512 ,  H01L2924/00

摘要： To provide a method, for manufacturing a thin semiconductor chip, in which the wafer is stably held during processing to maintain a stable shape and to avoid generation of cracks on the wafer. When a thin wafer (1) having a surface (1a) thereon is to be processed, the method comprising the steps of: adhering a rigid support body (2) to the other surface (1b) of the thin wafer (1); and adhering a ring-shaped frame (3) encircling an outer periphery of the thin wafer to the rigid support body (2).

摘要翻译： 为了提供一种用于制造薄半导体芯片的方法，其中在处理期间晶片被稳定地保持以保持稳定的形状并且避免在晶片上产生裂纹。 当要处理其上具有表面（1a）的薄晶片（1）时，该方法包括以下步骤：将刚性支撑体（2）粘附到薄晶片（1）的另一表面（1b） ; 并且将围绕所述薄晶片的外周的环状框架（3）粘附到所述刚性支撑体（2）。

公开(公告)号：US06774467B2

公开(公告)日：2004-08-10

申请号：US09812276

申请日：2001-03-20

申请人： Michio Horiuchi ,  Takashi Kurihara ,  Tomio Nagaoka ,  Masao Aoki ,  Shigeru Mizuno

发明人： Michio Horiuchi ,  Takashi Kurihara ,  Tomio Nagaoka ,  Masao Aoki ,  Shigeru Mizuno

IPC分类号： H01L23495

CPC分类号： H01L24/81 ,  H01L21/561 ,  H01L21/563 ,  H01L23/24 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/29 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13339 ,  H01L2224/13347 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/29111 ,  H01L2224/2929 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/97 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/15747 ,  H01L2924/1579 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/01083 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0665

摘要： Thin semiconductor device, especially a thin package, which reduces and achieves uniform mounting height, not requiring mounting of individual chips, improves manufacturing yield, without being affected by variation in chip thickness, enables testing alltogether, and process for producing same, the semiconductor mounted with back surface exposed upward, on top of an insulating substrate having throughholes in thickness direction, the area around semiconductor side surfaces being sealed by a resin layer, metal interconnections on the bottom surface of the substrate define bottom portions of throughholes of the substrate, a solder resist layer having throughholes in the thickness direction covers the bottom surface of metal interconnections and substrate, terminals extending downward from the active surface of the semiconductor are inserted into throughholes of the substrate, conductive filler fills gaps between the terminals and the throughholes of the substrate, and connection terminal and interconnections are electrically connected.

摘要翻译： 薄型半导体器件，特别是薄封装，其减少并实现均匀的安装高度，而不需要安装单个芯片，提高了制造成品率，而不受芯片厚度变化的影响，能够进行全面测试，以及制造工艺，半导体安装 背面向上露出，在厚度方向上具有通孔的绝缘基板的顶部，半导体侧面的周围的区域被树脂层密封，在基板的底面上的金属互连限定了基板的通孔的底部， 在厚度方向上具有通孔的阻焊层覆盖金属互连和基板的底面，从半导体的有源表面向下延伸的端子插入到基板的通孔中，导电填料填充端子之间的间隙和基板的通孔 ，连接终端 并且互连电连接。

公开(公告)号：US06663714B2

公开(公告)日：2003-12-16

申请号：US09858239

申请日：2001-05-17

申请人： Shigeru Mizuno ,  Hiroshi Doi ,  Seiji Itani ,  Xiao-Meng Liu

发明人： Shigeru Mizuno ,  Hiroshi Doi ,  Seiji Itani ,  Xiao-Meng Liu

IPC分类号： H01L2100

CPC分类号： C23C16/45508 ,  C23C16/4412 ,  C23C16/45521 ,  C23C16/4585 ,  C23C16/54 ,  H01L21/28556 ,  Y10S156/915

摘要： The present invention is to provide a CVD apparatus having a high productivity, involving less contamination on the back surface of a substrate and having a high yield. A CVD apparatus for forming a thin film is characterized in that the interior of the vessel is divided into a upper portion and a lower portion (transfer chamber) by a support member for holding the ring chuck and the upper portion is further divide by inner wall into a deposition chamber and an exhaust chamber in axial symmetry around the same central axis. The deposition chamber communicated to the exhaust chamber through a gap between the inner wall and the ring chuck and/or holes provided in the inner wall. The transfer chamber is communicated to the deposition chamber or exhaust chamber through a gap formed between the ring chuck and the support member.

摘要翻译： 本发明提供一种具有高生产率的CVD装置，其具有较低的基板背面的污染并且具有高的收率。1。一种用于形成薄膜的CVD装置，其特征在于将容器的内部分成 通过用于保持环卡盘和上部的支撑构件的上部和下部（传送室）进一步被内壁分隔成围绕同一中心轴线的对称的沉积室和排气室。沉积室 通过内壁和环形夹头之间的间隙和/或设置在内壁中的孔与排气室相通。 传送室通过形成在环形卡盘和支撑构件之间的间隙而连通到沉积室或排气室。

公开(公告)号：US06348238B1

公开(公告)日：2002-02-19

申请号：US09453883

申请日：2000-02-15

申请人： Shigeru Mizuno ,  Makoto Satou ,  Manabu Tagami ,  Hideki Satou

发明人： Shigeru Mizuno ,  Makoto Satou ,  Manabu Tagami ,  Hideki Satou

IPC分类号： C23C1432

CPC分类号： H01J37/32706 ,  C23C14/354 ,  H01J37/3405

摘要： A thin film is fabricated while causing ions in a plasma P to be incident by effecting biasing relative to the space potential of the plasma P by imparting a set potential to the surface of a substrate 9. A bias system 6 causes the substrate surface potential Vs to vary in pulse form by imposing an electrode imposed voltage Ve in pulse form on a bias electrode 23 which is in a dielectric block 22. The pulse frequency is lower than the oscillation frequency of ions in the plasma P, and the pulse period T, pulse width t and pulse height h are controlled by a control section 62 in a manner such that the incidence of ions is optimized. The imposed pulses are controlled in a manner such that the substrate surface potential Vs recovers to a floating potential Vf at the end of a pulse period T, and that the ion incidence energy temporarily crosses a thin film sputtering threshold value in a pulse period T.

摘要翻译： 制造薄膜，同时使等离子体P中的离子通过相对于等离子体P的空间电位施加偏置而入射，通过给基板9的表面赋予设定电位。偏置系统6使基板表面电位Vs 通过在介质块22中的偏置电极23上施加脉冲形式的电极施加的电压Ve来改变脉冲形式。脉冲频率低于等离子体P中的离子的振荡频率，脉冲周期T， 脉冲宽度t和脉冲高度h由控制部分62以使得离子的入射被优化的方式控制。 施加的脉冲以使得在脉冲周期T结束时基板表面电位Vs恢复到浮动电位Vf的方式被控制，并且离子入射能量在脉冲周期T中暂时跨越薄膜溅射阈值。