公开(公告)号：US20190206458A1

公开(公告)日：2019-07-04

申请号：US16222909

申请日：2018-12-17

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC: G11C8/12 ,  G11C5/06 ,  G11C5/04 ,  G11C5/02 ,  G11C8/18 ,  G11C7/10 ,  H01L23/00 ,  H01L25/065

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/18 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

公开(公告)号：US10209922B2

公开(公告)日：2019-02-19

申请号：US14806788

申请日：2015-07-23

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Vlad Fruchter ,  Lawrence Lai ,  Pradeep Batra ,  Steven C. Woo ,  Wayne Frederick Ellis

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/06 ,  G11C7/10

Abstract: A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer.

公开(公告)号：US20190027210A1

公开(公告)日：2019-01-24

申请号：US16139636

申请日：2018-09-24

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C11/406 ,  G11C11/4074 ,  G06F1/32 ,  G11C29/02 ,  G11C7/02 ,  G11C11/4072 ,  G11C7/20

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US20180226120A1

公开(公告)日：2018-08-09

申请号：US15855535

申请日：2017-12-27

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C11/406 ,  G11C11/4074

CPC classification number: G11C11/40615 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/022 ,  G11C29/028

Abstract: In one embodiment, a memory device includes a clock receiver to receive a clock signal and a plurality of mode registers to store parameter information associated with a plurality of operating clock frequencies of the clock signal. The plurality of clock frequencies include a first clock frequency and a second clock frequency. The memory device also includes a command interface to receive commands synchronously with respect to the clock signal. The command interface receives a command that instructs the DRAM device to change operation from the first clock frequency to the second clock frequency.

公开(公告)号：US09921751B2

公开(公告)日：2018-03-20

申请号：US15000306

申请日：2016-01-19

Applicant: Rambus Inc.

Inventor： Richard E. Perego ,  Pradeep Batra ,  Steven Woo ,  Lawrence Lai ,  Chi-Ming Yeung

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/10 ,  G06F13/38 ,  G06F12/06 ,  G11C7/10 ,  G11C14/00 ,  G06F12/00 ,  G06F13/42

CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0685 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/10 ,  G06F13/385 ,  G06F13/4239 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/251 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C7/1072 ,  G11C14/0018 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

公开(公告)号：US09898400B2

公开(公告)日：2018-02-20

申请号：US15497126

申请日：2017-04-25

Applicant: Rambus Inc.

Inventor： Thomas A. Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/02 ,  G11C7/10 ,  G11C7/22 ,  G11C8/10

CPC classification number: G06F12/023 ,  G06F2212/2024 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/22 ,  G11C8/10 ,  G11C2207/107

Abstract: A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

公开(公告)号：US20170293552A1

公开(公告)日：2017-10-12

申请号：US15497126

申请日：2017-04-25

Applicant: Rambus Inc.

Inventor： Thomas A. Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

IPC: G06F12/02 ,  G11C7/22 ,  G11C8/10 ,  G11C7/10

CPC classification number: G06F12/023 ,  G06F2212/2024 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/22 ,  G11C8/10 ,  G11C2207/107

Abstract: A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

公开(公告)号：US09734879B2

公开(公告)日：2017-08-15

申请号：US14813028

申请日：2015-07-29

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC: G11C5/06 ,  G11C8/12 ,  G11C5/02 ,  G11C8/18 ,  G11C5/04 ,  G11C7/10 ,  H01L23/00 ,  H01L25/065

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/18 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

公开(公告)号：US20150324309A1

公开(公告)日：2015-11-12

申请号：US14806788

申请日：2015-07-23

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Vlad Fruchter ,  Lawrence Lai ,  Pradeep Batra ,  Steven C. Woo ,  Wayne Frederick Ellis

IPC: G06F13/28 ,  G11C7/10 ,  G06F13/16

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0671 ,  G06F12/06 ,  G06F13/16 ,  G06F13/1621 ,  G06F13/1626 ,  G06F13/1668 ,  G11C7/10

Abstract: A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer.

Abstract translation: 通过存储器接口连接到存储器控制器的模块的存储器空间可以用作命令缓冲器。 模块通过命令缓冲区接收的命令由模块执行。 存储器控制器可以无序地写入命令缓冲器。 存储器控制器可能会延迟或消除对命令缓冲区的写入。 与命令关联的标签用于指定执行顺序命令。 模块的存储空间中的状态缓冲区用于通信是否接收或执行了命令。 通过状态缓冲器接收的信息可以用作确定将命令重新发送到命令缓冲区的基础。

公开(公告)号：US09043513B2

公开(公告)日：2015-05-26

申请号：US14574156

申请日：2014-12-17

Applicant: Rambus Inc.

Inventor： Richard E. Perego ,  Pradeep Batra ,  Steven Woo ,  Lawrence Lai ,  Chi-Ming Yeung

IPC: G06F9/26 ,  G06F12/02 ,  G06F12/10 ,  G06F13/42 ,  G06F12/00

CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0685 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/10 ,  G06F13/385 ,  G06F13/4239 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/251 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C7/1072 ,  G11C14/0018 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

Abstract translation: 存储器系统包括将命令和地址传送到主存储器模块的CPU。 该模块包括缓冲电路，用于中继CPU和主存储器之间的命令和数据。 存储器模块还包括嵌入式处理器，其共享对主存储器的访问以支持外围功能，例如图形处理，以改善整体系统性能。 缓冲电路有助于CPU和外围处理器之间的指令和数据通信，以最小化或消除修改CPU的需要，从而减少采用具有集成处理能力的主存储器模块的实际障碍。