公开(公告)号：US09673311B1

公开(公告)日：2017-06-06

申请号：US15182405

申请日：2016-06-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Peter Moens ,  Jia Guo ,  Ali Salih ,  Chun-Li Liu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/20 ,  H01L29/778 ,  H01L29/205 ,  H01L21/02

CPC classification number: H01L29/7783 ,  H01L21/0254 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/66431 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7782 ,  H01L29/7787 ,  H01L2924/13064

Abstract: An electronic device can include a HEMT including at least two channel layers. In an embodiment, a lower semiconductor layer overlies a lower channel layer, wherein the lower semiconductor layer has an aluminum content that is at least 10% of a total metal content of the lower semiconductor layer. An upper semiconductor layer overlies the upper channel layer, wherein the upper semiconductor layer has an aluminum content that is greater as compared to the lower semiconductor layer. In another embodiment, an electronic device can include stepped source and drain electrodes, so that lower contact resistance can be achieved. In a further embodiment, an absolute value of a difference between pinch-off or threshold voltages between different channel layers is greater than 1 V and allows current to be turned on or turned off for a channel layer without affecting another channel layer.

公开(公告)号：US09653387B2

公开(公告)日：2017-05-16

申请号：US15204197

申请日：2016-07-07

Applicant: Semiconductor Components Industries, LLC

Inventor： Balaji Padmanabhan ,  Prasad Venkatraman ,  Ali Salih

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49562 ,  H01L21/4825 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49558 ,  H01L23/49575 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2224/37099

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead, a second lead, and a third lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure. The first semiconductor chip is configured from a silicon semiconductor material and has a gate bond pad, a source bond pad, and a drain bond pad, and the second semiconductor chip is configured from a gallium nitride semiconductor chip and has a gate bond pad, a source bond pad, and a drain bond pad. In accordance with another embodiment, a method for manufacturing a semiconductor component includes coupling a first semiconductor chip to a support and coupling a second semiconductor chip to the support.

公开(公告)号：US09627530B2

公开(公告)日：2017-04-18

申请号：US14452222

申请日：2014-08-05

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li Liu ,  Balaji Padmanabhan ,  Ali Salih ,  Peter Moens

IPC: H01L21/02 ,  H01L29/78 ,  H01L21/762 ,  H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L21/74 ,  H01L21/76 ,  H01L29/778 ,  H01L29/20 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7827 ,  H01L21/743 ,  H01L21/746 ,  H01L21/7605 ,  H01L21/76224 ,  H01L21/763 ,  H01L21/76898 ,  H01L29/0607 ,  H01L29/0649 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/66318 ,  H01L29/66462 ,  H01L29/66666 ,  H01L29/7786

Abstract: In accordance with an embodiment, a method for manufacturing a semiconductor component includes forming a first trench through a plurality of layers of compound semiconductor material. An insulating material is formed on first and second sidewalls of the first trench and first and second sidewalls of the second trench and a trench fill material is formed in the first and second trenches. In accordance with another embodiment, the semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.

公开(公告)号：US20170025403A1

公开(公告)日：2017-01-26

申请号：US15197255

申请日：2016-06-29

Applicant: Semiconductor Components Industries, LLC

Inventor： Balaji Padmanabhan ,  Prasad Venkatraman ,  Chun-Li Liu ,  Ali Salih

IPC: H01L27/02 ,  H01L29/16 ,  H01L29/861 ,  H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L21/8258

CPC classification number: H01L27/0266 ,  H01L21/8258 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/7787 ,  H01L29/861

Abstract: In accordance with an embodiment, semiconductor component having a compound semiconductor material based semiconductor device connected to a silicon based semiconductor device and a protection element, wherein the silicon based semiconductor device is a transistor. The protection element is coupled in parallel across the silicon based semiconductor device and may be a resistor, a diode, or a transistor. In accordance with another embodiment, the silicon based semiconductor device is a diode. The compound semiconductor material may be shorted to a source of potential such as, for example, ground, with a shorting element.

Abstract translation: 根据实施例，具有连接到硅基半导体器件的化合物半导体材料基半导体器件和保护元件的半导体部件，其中硅基半导体器件是晶体管。 保护元件在硅​​基半导体器件上并联耦合，并且可以是电阻器，二极管或晶体管。 根据另一个实施例，硅基半导体器件是二极管。 化合物半导体材料可以用短路元件短路到诸如地面的电位源。

公开(公告)号：US20170025340A1

公开(公告)日：2017-01-26

申请号：US15208703

申请日：2016-07-13

Applicant: Semiconductor Components Industries, LLC

Inventor： Balaji Padmanabhan ,  Prasad Venkatraman ,  Ali Salih ,  Chun-Li Liu ,  Phillip Celaya

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49575 ,  H01L21/4825 ,  H01L21/4882 ,  H01L23/3735 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49568 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2224/37099

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead and a second lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure. The first semiconductor chip is configured from a silicon semiconductor material and has a gate bond pad, a source bond pad, and a drain bond pad, and the second semiconductor chip is configured from a gallium nitride semiconductor chip and has a gate bond pad, a source bond pad, and a drain bond pad. In accordance with another embodiment, a method for manufacturing a semiconductor component includes coupling a first semiconductor chip to a support and coupling a second semiconductor chip to the support.

Abstract translation: 根据实施例，半导体部件包括具有第一器件接收结构的支撑件，第二器件接收结构，第一引线和第二引线。 第一半导体芯片耦合到第一器件接收结构，第二半导体芯片耦合到第一半导体芯片和第二器件接收结构。 第一半导体芯片由硅半导体材料构成，具有栅极接合焊盘，源极接合焊盘和漏极接合焊盘，第二半导体芯片由氮化镓半导体芯片构成，具有栅极接合焊盘， 源极接合焊盘和漏极接合焊盘。 根据另一实施例，一种用于制造半导体部件的方法包括：将第一半导体芯片耦合到支撑件并将第二半导体芯片耦合到支撑件。

公开(公告)号：US09553165B2

公开(公告)日：2017-01-24

申请号：US15176603

申请日：2016-06-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. Grivna ,  Ali Salih

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L21/265 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/762 ,  H01L29/417

CPC classification number: H01L29/66333 ,  H01L21/265 ,  H01L21/3043 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/76224 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/7397

Abstract: In one embodiment, an IGBT is formed to include a plurality of termination trenches in a termination region of the IGBT. An embodiment may include that one end of one or more termination trenches may be exposed on one surface of the semiconductor device.

Abstract translation: 在一个实施例中，IGBT形成为在IGBT的端接区域中包括多个端接沟槽。 一个实施例可以包括一个或多个终止沟槽的一端可以暴露在半导体器件的一个表面上。

公开(公告)号：US09460995B2

公开(公告)日：2016-10-04

申请号：US14939873

申请日：2015-11-12

Applicant: Semiconductor Components Industries, LLC

Inventor： Ali Salih ,  Chun-Li Liu ,  Gordon M. Grivna

IPC: H01L29/49 ,  H01L23/522 ,  H01L29/66 ,  H01L29/778 ,  H01L21/768 ,  H01L23/498 ,  H01L21/78 ,  H01L23/482 ,  H01L23/532 ,  H01L29/20 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/4824 ,  H01L23/49827 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/84 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L2221/68327 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/04034 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/37012 ,  H01L2224/37013 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/3716 ,  H01L2224/37187 ,  H01L2224/3719 ,  H01L2224/37639 ,  H01L2224/37644 ,  H01L2224/37647 ,  H01L2224/37655 ,  H01L2224/37664 ,  H01L2224/40499 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/07811 ,  H01L2224/45099

Abstract: In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors.

Abstract translation: 在一个实施例中，形成HEMT器件的方法可以包括将导体或多个导体电镀到覆盖在HEMT器件的多个载流电极上的绝缘体上。 该方法还可以包括将连接器附接到导体上或者将多个连接器附接到多个导体上。

公开(公告)号：US20160043219A1

公开(公告)日：2016-02-11

申请号：US14452222

申请日：2014-08-05

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li Liu ,  Balaji Padmanabhan ,  Ali Salih ,  Peter Moens

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/417 ,  H01L29/40 ,  H01L29/66 ,  H01L29/20 ,  H01L29/06 ,  H01L21/762 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L29/7827 ,  H01L21/743 ,  H01L21/746 ,  H01L21/7605 ,  H01L21/76224 ,  H01L21/763 ,  H01L21/76898 ,  H01L29/0607 ,  H01L29/0649 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/66318 ,  H01L29/66462 ,  H01L29/66666 ,  H01L29/7786

Abstract: In accordance with an embodiment, a method for manufacturing a semiconductor component includes forming a first trench through a plurality of layers of compound semiconductor material. An insulating material is formed on first and second sidewalls of the first trench and first and second sidewalls of the second trench and a trench fill material is formed in the first and second trenches. In accordance with another embodiment, the semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.

公开(公告)号：US20160043178A1

公开(公告)日：2016-02-11

申请号：US14452130

申请日：2014-08-05

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li Liu ,  Ali Salih

IPC: H01L29/10 ,  C30B23/02 ,  C30B19/12 ,  H01L21/02 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/205 ,  C30B25/18 ,  C30B29/40

CPC classification number: H01L21/0254 ,  C30B19/12 ,  C30B23/025 ,  C30B25/183 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02507 ,  H01L21/0257 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/36 ,  H01L29/7786

Abstract: In accordance with an embodiment, a method for manufacturing a semiconductor component includes providing a semiconductor material having a surface, forming an epitaxial layer of carbon doped semiconductor material on the semiconductor substrate, the epitaxial layer having a surface, forming a nucleation layer on the epitaxial layer; and forming a layer of III-nitride material on the nucleation layer. In accordance with another embodiment, the semiconductor component includes a silicon semiconductor substrate of a first conductivity type; a carbon doped epitaxial layer on the silicon semiconductor substrate; a buffer layer over the carbon doped buffer layer; and a channel layer on the buffer layer.

Abstract translation: 根据实施例，制造半导体部件的方法包括提供具有表面的半导体材料，在半导体衬底上形成掺杂碳的半导体材料的外延层，所述外延层具有表面，在外延层上形成成核层 层; 并在成核层上形成III族氮化物材料层。 根据另一实施例，半导体部件包括第一导电类型的硅半导体衬底; 在硅半导体衬底上的碳掺杂外延层; 在碳掺杂缓冲层上的缓冲层; 以及缓冲层上的通道层。

公开(公告)号：US20140264456A1

公开(公告)日：2014-09-18

申请号：US14208803

申请日：2014-03-13

Applicant: Semiconductor Components Industries, LLC

Inventor： Ali Salih ,  John Michael Parsey, JR.

IPC: H01L29/778 ,  H01L21/02

CPC classification number: H01L29/778 ,  H01L21/02365 ,  H01L21/187 ,  H01L21/6835 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7789 ,  H01L2221/68368

Abstract: In an embodiment, a semiconductor device is formed by a method that includes, providing a base substrate of a first semiconductor material, and forming a layer that is one of SiC or a III-V series material on the base substrate. In a different embodiment, the base substrate may be one of silicon, porous silicon, or porous silicon with nucleation sites formed thereon, or silicon in a (111) plane.

Abstract translation: 在一个实施例中，通过一种方法形成半导体器件，该方法包括提供第一半导体材料的基底衬底，并在基底衬底上形成作为SiC或III-V系列材料之一的层。 在不同的实施例中，基底可以是其中形成有成核位点的硅，多孔硅或多孔硅中的一种，或（111）面内的硅。