公开(公告)号：US10957597B2

公开(公告)日：2021-03-23

申请号：US16867836

申请日：2020-05-06

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Michael J. Seddon

IPC分类号： H01L21/78 ,  H01L21/04

摘要： Implementations of methods of cutting a semiconductor substrate may include aligning a first saw blade substantially perpendicularly with a crystal plane of a non-cubic crystalline lattice of a semiconductor substrate coupled with a backmetal layer and cutting through at least a majority of the semiconductor substrate at an angle substantially perpendicular with the crystal plane of the non-cubic crystalline lattice of the semiconductor substrate. The method may also include aligning a second saw blade substantially perpendicularly with the semiconductor substrate and cutting entirely through the semiconductor substrate and the backmetal layer using the second saw blade.

公开(公告)号：US10825731B2

公开(公告)日：2020-11-03

申请号：US16506004

申请日：2019-07-09

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Michael J. Seddon ,  Takashi Noma

IPC分类号： H01L21/78 ,  H01L21/66 ,  H01L21/3205 ,  H01L21/683 ,  H01L21/02 ,  H01L21/304

摘要： Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.

公开(公告)号：US10741487B2

公开(公告)日：2020-08-11

申请号：US15961642

申请日：2018-04-24

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Michael J. Seddon ,  Mark Griswold

IPC分类号： H01L21/76 ,  H01L23/522 ,  H01L23/34 ,  H01L21/786 ,  H01L21/02 ,  H01L23/12

摘要： Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.

公开(公告)号：US10685863B2

公开(公告)日：2020-06-16

申请号：US15964464

申请日：2018-04-27

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Michael J. Seddon

IPC分类号： H01L21/683 ,  B24B7/22 ,  H01L25/00

摘要： Implementations of systems for thinning a semiconductor substrate may include: a substrate chuck configured to receive a semiconductor substrate for thinning, a spindle, a grinding wheel coupled to the spindle, and a water medium configured to be in contact with the semiconductor substrate during thinning. An ultrasonic energy source may be directly coupled to the substrate chuck, the spindle, the grinding wheel, the water medium, or any combination thereof.

公开(公告)号：US10679898B2

公开(公告)日：2020-06-09

申请号：US16674780

申请日：2019-11-05

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Michael J. Seddon

IPC分类号： H01L21/78 ,  H01L21/04

摘要： Implementations of methods of cutting a semiconductor substrate may include aligning a first saw blade substantially perpendicularly with a crystal plane of a non-cubic crystalline lattice of a semiconductor substrate coupled with a backmetal layer and cutting through at least a majority of the semiconductor substrate at an angle substantially perpendicular with the crystal plane of the non-cubic crystalline lattice of the semiconductor substrate. The method may also include aligning a second saw blade substantially perpendicularly with the semiconductor substrate and cutting entirely through the semiconductor substrate and the backmetal layer using the second saw blade.

公开(公告)号：US10589989B2

公开(公告)日：2020-03-17

申请号：US15782758

申请日：2017-10-12

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Michael J. Seddon

IPC分类号： B81B7/00 ,  B81B3/00 ,  G01L9/00 ,  G01L13/02 ,  G01L9/06

摘要： Implementations of absolute pressure sensor devices may include a microelectromechanical system (MEMS) absolute pressure sensor coupled over a controller die. The MEMS absolute pressure sensor may be mechanically coupled to the controller die and may also be configured to electrically couple with the controller die. A perimeter of the controller die may be one of the same size and larger than a perimeter of the MEMS absolute pressure sensor. The controller die may be configured to electrically couple with a module through an electrical connector.

公开(公告)号：US10446480B2

公开(公告)日：2019-10-15

申请号：US16101259

申请日：2018-08-10

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Michael J. Seddon ,  Francis J. Carney

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/3065 ,  H01L21/78 ,  H01L23/495 ,  H01L21/67 ,  H01L21/66 ,  H01L21/56 ,  H01L23/31 ,  H02M3/158 ,  H01L23/482 ,  H01L25/065 ,  H01L25/00 ,  H01L23/544 ,  H01L23/00 ,  H01L21/02 ,  H01L21/304 ,  H01L21/308 ,  H01L27/146 ,  H01L21/288 ,  H01L21/683 ,  H01L21/768 ,  H01L23/48 ,  H01L27/02 ,  H01L27/088 ,  H01L27/14 ,  H01L29/08 ,  H01L23/15 ,  H01L23/14 ,  H01L23/367

摘要： A through-substrate vias structure includes a substrate having opposing first and second major surfaces. One or more conductive via structures are disposed extending from the first major surface to a first vertical distance within the substrate. A recessed region extends from the second major surface to a second vertical distance within the substrate and adjoining a lower surface of the conductive via. In one embodiment, the second vertical distance is greater than the first vertical distance. A conductive region is disposed within the recessed region and is configured to be in electrical and/or thermal communication with the conductive via.

公开(公告)号：US10199316B2

公开(公告)日：2019-02-05

申请号：US15817423

申请日：2017-11-20

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Michael J. Seddon ,  Francis J. Carney

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/3065 ,  H01L21/78 ,  H01L23/495 ,  H01L21/67 ,  H01L21/66 ,  H01L21/56 ,  H01L23/31 ,  H02M3/158 ,  H01L23/482 ,  H01L25/065 ,  H01L25/00 ,  H01L23/544 ,  H01L23/00 ,  H01L21/02 ,  H01L21/304 ,  H01L21/308 ,  H01L27/146 ,  H01L21/288 ,  H01L21/683 ,  H01L21/768 ,  H01L23/48 ,  H01L27/02 ,  H01L27/088 ,  H01L27/14 ,  H01L29/08 ,  H01L23/15

摘要： A semiconductor device has a first semiconductor wafer. The first semiconductor wafer is singulated to provide a first wafer section including at least one first semiconductor die or a plurality of first semiconductor die. The first wafer section is a fractional portion of the first semiconductor wafer. An edge support structure is formed around the first wafer section. A second wafer section includes at least one second semiconductor die. The second wafer section can be an entire second semiconductor wafer. The first semiconductor die is a first type of semiconductor device and the second semiconductor die is a second type of semiconductor device. An alignment opening is formed through the first wafer section and second wafer section with a light source projected through the opening. The first wafer section is bonded to the second wafer section with the first semiconductor die aligned with the second semiconductor die.

公开(公告)号：US10079199B2

公开(公告)日：2018-09-18

申请号：US15244737

申请日：2016-08-23

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Michael J. Seddon ,  Francis J. Carney

IPC分类号： H01L23/498 ,  H01L23/495 ,  H01L23/482 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/3065 ,  H01L23/544 ,  H01L21/308 ,  H01L21/67 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78 ,  H01L21/66 ,  H02M3/158 ,  H01L21/02 ,  H01L21/304 ,  H01L27/146

CPC分类号： H01L23/49827 ,  H01L21/02035 ,  H01L21/288 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/67069 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/12 ,  H01L22/26 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/4822 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/544 ,  H01L23/562 ,  H01L24/00 ,  H01L24/05 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/14 ,  H01L27/14625 ,  H01L27/14683 ,  H01L27/14685 ,  H01L29/0847 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/13055 ,  H01L2924/13091 ,  H02M3/158

摘要： A through-substrate vias structure includes a substrate having opposing first and second major surfaces. One or more conductive via structures are disposed extending from the first major surface to a first vertical distance within the substrate. A recessed region extends from the second major surface to a second vertical distance within the substrate and adjoining a lower surface of the conductive via. In one embodiment, the second vertical distance is greater than the first vertical distance. A conductive region is disposed within the recessed region and is configured to be in electrical and/or thermal communication with the conductive via.

公开(公告)号：US09847310B2

公开(公告)日：2017-12-19

申请号：US14812861

申请日：2015-07-29

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Michael J. Seddon ,  Francis J. Carney

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498

CPC分类号： H01L24/17 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13294 ,  H01L2224/13311 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16245 ,  H01L2224/16503 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81211 ,  H01L2224/81411 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/97 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2224/81

摘要： A method of bonding a plurality of die having first and second metal layers on a die surface to a board, comprising placing a first die onto a board comprising one of a ceramic or substrate board or metal lead frame having a solderable surface and placing the first die and the board into a reflow oven. The method includes reflowing at a first reflow temperature for a first period until the first metal board layer and at least one of the first and second metal die layers of the first die form an alloy to adhere the first die to the board. The newly formed alloy has a higher melting temperature than the first reflow temperature. Accordingly, additional die may be reflowed and attached to the board without causing the bonding of the first die to the board to fail if the same reflow temperature is used.