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    Method of making a semiconductor device with barrier and conductor protection
    63.
    发明授权
    Method of making a semiconductor device with barrier and conductor protection 失效
    制造具有屏障和导体保护的半导体器件的方法

    公开(公告)号：US6130150A

    公开(公告)日：2000-10-10

    申请号：US370523

    申请日：1999-08-06

    申请人： Sailesh Mansinh Merchant ,  Sudhanshu Misra ,  Pradip Kumar Roy

    发明人： Sailesh Mansinh Merchant ,  Sudhanshu Misra ,  Pradip Kumar Roy

    IPC分类号： H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/76819 ,  H01L21/76802 ,  H01L21/76831

    摘要： A method of making a semiconductor device includes forming at least one opening, having vertical sidewalls and a bottom, in a first dielectric layer adjacent a substrate. A second dielectric layer is formed to line the vertical sidewalls of the at least one opening, and has a relatively lower etch rate than the first dielectric layer. A conductive layer is deposited to fill the at least one opening and an upper surface of the semiconductor wafer is cleaned. The method preferably includes the steps of depositing a barrier layer lining the second dielectric layer and the bottom of the at least one opening, and chemically mechanically polishing the semiconductor wafer with the second dielectric layer protecting upper edges of the barrier layer and conductive layer. Preferably, the relatively lower etch rate of the second dielectric layer is a relatively lower wet etch rate based on a wet etch in hydrofluoric acid and the step of cleaning the upper surface of the semiconductor wafer comprises a wet etch in hydrofluoric acid. Thus, the conductive layer and the barrier layer are protected from a cleaning wet etch which may include the use of hydrofluoric acid. Localized corrosion of the conductive layer, which may be copper, is prevented.

    摘要翻译： 制造半导体器件的方法包括在邻近衬底的第一电介质层中形成具有垂直侧壁和底部的至少一个开口。 形成第二电介质层以使所述至少一个开口的垂直侧壁成线，并且具有比所述第一电介质层相对较低的蚀刻速率。 沉积导电层以填充至少一个开口，并清洁半导体晶片的上表面。 该方法优选包括以下步骤：沉积衬在第二介电层和至少一个开口的底部的阻挡层，以及用保护阻挡层和导电层的上边缘的第二介电层化学机械抛光半导体晶片。 优选地，基于氢氟酸中的湿蚀刻，第二电介质层的相对较低的蚀刻速率是相对较低的湿蚀刻速率，并且清洁半导体晶片的上表面的步骤包括在氢氟酸中的湿蚀刻。 因此，导电层和阻挡层被保护免受可能包括使用氢氟酸的清洁湿法蚀刻。 防止可能是铜的导电层的局部腐蚀。

    Methods for fabricating a metal-oxide-metal capacitor
    68.
    发明授权
    Methods for fabricating a metal-oxide-metal capacitor 有权
    制造金属氧化物 - 金属电容器的方法

    公开(公告)号：US06730601B2

    公开(公告)日：2004-05-04

    申请号：US10080186

    申请日：2002-02-21

    申请人： Edward Belden Harris ,  Yifeng Winston Yan ,  Sailesh Mansinh Merchant

    发明人： Edward Belden Harris ,  Yifeng Winston Yan ,  Sailesh Mansinh Merchant

    IPC分类号： H01L2144

    CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L21/76807

    摘要： A method of fabricating a metal-oxide-metal capacitor in a microelectronic device is provided. First, a recess is formed in a surface of a dielectric layer deposited over a microelectronic substrate. A first barrier layer is then deposited over the dielectric layer such that the first barrier layer conforms to the recess. A first conductive element is then deposited over the first barrier layer so as to at least fill the recess. A second barrier layer is further deposited over the first conductive element such that the first barrier layer and the second barrier layer cooperate to encapsulate the first conductive element. The first conductive element thus comprises a first plate of the capacitor. A capacitor dielectric layer is then deposited over the second barrier layer, followed by the deposition of a second conductive element over the capacitor dielectric layer. The second conductive element thus comprises a second plate of the capacitor. In one embodiment, the dielectric layer may be comprised of an oxide and the barrier layers are comprised of, for example, tantalum; tantalum nitride; titanium nitride; tungsten nitride; silicon nitrides of tantalum, titanium, and tungsten; and combinations thereof. The first conductive element is preferably comprised of copper. The capacitor dielectric may be comprised of an oxide or tantalum pentoxide, while the second conductive element may be comprised of a layer of an aluminum alloy disposed between two barrier layers, each comprised of, for example, tantalum; tantalum nitride; titanium nitride; tungsten nitride; silicon nitrides of tantalum, titanium, and tungsten; and combinations thereof. Associated apparatuses are also provided.

    摘要翻译： 提供了一种在微电子器件中制造金属氧化物 - 金属电容器的方法。 首先，在沉积在微电子衬底上的电介质层的表面上形成凹部。 然后在电介质层上沉积第一阻挡层，使得第一阻挡层符合凹陷。 然后将第一导电元件沉积在第一阻挡层上，以便至少填充凹部。 第二阻挡层进一步沉积在第一导电元件上，使得第一阻挡层和第二阻挡层协作以封装第一导电元件。 因此，第一导电元件包括​​电容器的第一板。 然后在第二阻挡层上沉积电容器电介质层，随后在电容器介电层上沉积第二导电元件。 因此，第二导电元件包括​​电容器的第二板。 在一个实施例中，电介质层可以由氧化物构成，并且阻挡层由例如钽构成; 氮化钽; 氮化钛; 氮化钨; 钽，钛和钨的氮化硅; 及其组合。 第一导电元件优选由铜构成。 电容器电介质可以由氧化物或五氧化二钽组成，而第二导电元件可以由设置在两个阻挡层之间的铝合金层组成，每个阻挡层由例如钽构成; 氮化钽; 氮化钛; 氮化钨; 钽，钛和钨的氮化硅; 及其组合。 还提供了相关装置。

    Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics
    69.
    发明授权
    Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics 有权
    集成电路金属间介质中的防扩散阻挡层

    公开(公告)号：US06727588B1

    公开(公告)日：2004-04-27

    申请号：US09377386

    申请日：1999-08-19

    申请人： Mahjoub Ali Abdelgadir ,  Nace Layadi ,  Sailesh Mansinh Merchant ,  Vivek Saxena ,  Pei H. Yih

    发明人： Mahjoub Ali Abdelgadir ,  Nace Layadi ,  Sailesh Mansinh Merchant ,  Vivek Saxena ,  Pei H. Yih

    IPC分类号： H01L2348

    CPC分类号： H01L23/5329 ,  H01L21/76829 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A cap or barrier layer that can prevent the migration of impurities in low dielectric constant material, thereby preventing the impurities from attacking conductive elements in subsequent levels of a multi-level integrated circuit structure. The integrated circuit by may be fabricated by disposing the diffusion-preventing barrier layer between a first dielectric layer and the conductive layer at an upper level of the integrated circuit. The diffusion preventing barrier layer may be formed in-situ over the impurity containing dielectric material with the subsequent disposition of a metal layer thereover, and further processing of a multi-layer dielectric structure to include polishing. The in-situ deposition of the cap or barrier layer prevents the exposure of the impurity containing layer to atmosphere, thereby avoiding contamination of the layer by moisture absorption, hydrogen absorption, or the like. In an exemplary embodiment, the diffusion preventing barrier layer is a material containing silicon oxide or silicon rich silicon oxide SiOx, where x is preferably less than 2.

    摘要翻译： 可以防止杂质在低介电常数材料中迁移的帽或阻挡层，从而防止杂质在多级集成电路结构的后续级别中侵袭导电元件。 集成电路可以通过在集成电路的上层设置第一介电层和导电层之间设置防扩散阻挡层来制造。 扩散防止阻挡层可以在含杂质的电介质材料上的原位形成，随后在其上布置金属层，并且进一步处理多层电介质结构以包括抛光。 帽或阻挡层的原位沉积防止了含杂质层暴露于大气中，从而避免了由吸湿，吸氢等引起的层的污染。 在示例性实施例中，防扩散阻挡层是含有氧化硅或富硅氧化硅SiO x的材料，其中x优选小于2。