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126 条记录 (耗时 0.036 秒)

    One transistor cell FeRAM memory array
    61.
    发明授权
    One transistor cell FeRAM memory array 失效
    一个晶体管单元FeRAM存储器阵列

    公开(公告)号：US06711049B1

    公开(公告)日：2004-03-23

    申请号：US10282985

    申请日：2002-10-28

    申请人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Fengyan Zhang ,  Nobuyoshi Awaya

    发明人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Fengyan Zhang ,  Nobuyoshi Awaya

    IPC分类号： G11C1122

    CPC分类号： G11C11/22

    摘要： A one-transistor FeRAM memory cell array includes an array of ferroelectric transistors arranged in rows and columns, each transistor having a source, a drain, a channel, a gate oxide layer over the channel and a ferroelectric stack formed on the gate oxide layer; word lines connecting the gate ferroelectric stack top electrodes of transistors in a row of the array; a connection to the channel of all transistors in the array formed by a substrate well; a set of first bit lines connecting the sources of all transistors in a column of the array; and a set of second bit lines connecting the drains of all transistors in a column of the array; wherein the ferroelectric stack has opposed edges, which, when projected to a level of the source, drain and channel, are coincident with an abutted edge of the source and the channel and the drain and the channel, respectively.

    摘要翻译： 单晶体管FeRAM存储单元阵列包括以行和列布置的铁电晶体管阵列，每个晶体管具有源极，漏极，沟道，沟道上的栅极氧化物层和形成在栅极氧化物层上的铁电堆叠; 连接阵列中的晶体管的栅极铁电叠层顶部电极的字线; 连接到由衬底阱形成的阵列中的所有晶体管的沟道; 连接阵列的列中的所有晶体管的源的一组第一位线; 以及连接阵列中的所有晶体管的漏极的一组第二位线; 其中所述铁电堆叠具有相对的边缘，当所述铁电堆叠被投影到所述源极的水平面时，所述漏极和沟道分别与所述源极和所述沟道以及所述漏极和所述沟道的邻接边缘重合。

    Single transistor ferroelectric transistor structure with high-K insulator and method of fabricating same
    63.
    发明授权
    Single transistor ferroelectric transistor structure with high-K insulator and method of fabricating same 失效
    具有高K绝缘体的单晶体管铁电晶体管结构及其制造方法

    公开(公告)号：US06602720B2

    公开(公告)日：2003-08-05

    申请号：US09820023

    申请日：2001-03-28

    申请人： Sheng Teng Hsu ,  Fengyan Zhang

    发明人： Sheng Teng Hsu ,  Fengyan Zhang

    IPC分类号： H01L2100

    CPC分类号： H01L29/4983 ,  H01L21/02189 ,  H01L21/02197 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/28291 ,  H01L21/31053 ,  H01L21/31604 ,  H01L21/31691 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/78391

    摘要： A ferroelectric transistor gate structure with a ferroelectric gate and a high-k insulator is provided. The high-k insulator may serve as both a gate dielectric and an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing a high-k insulator, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.

    摘要翻译： 提供了具有铁电栅极和高k绝缘体的铁电晶体管栅极结构。 高k绝缘体可以用作栅极电介质和绝缘体，以减少或消除氧或氢扩散到铁电栅极中。 还提供了形成铁电栅极结构的方法。 该方法包括以下步骤：形成牺牲栅极结构，去除牺牲栅极结构，沉积高k绝缘体，沉积铁电材料，使用CMP抛光铁电材料，以及形成覆盖铁电材料的顶部电极。

    Method of forming iridium conductive electrode/barrier structure
    64.
    发明授权
    Method of forming iridium conductive electrode/barrier structure 失效

    公开(公告)号：US06555456B2

    公开(公告)日：2003-04-29

    申请号：US10037192

    申请日：2001-11-09

    申请人： Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

    发明人： Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

    IPC分类号： H01L213205

    CPC分类号： H01L29/456 ,  H01L21/28291 ,  H01L28/55 ,  H01L28/65

    摘要： A conductive barrier, useful as a ferroelectric capacitor electrode, having high temperature stability has been provided. This conductive barrier permits the use of iridium (Ir) metal in IC processes involving annealing. Separating silicon substrate from Ir film with an intervening, adjacent, tantalum (Ta) film has been found to very effective in suppressing diffusion between layers. The Ir prevents the interdiffusion of oxygen into the silicon during annealing. A Ta or TaN layer prevents the diffusion of Ir into the silicon. This Ir/TaN structure protects the silicon interface so that adhesion, conductance, hillock, and peeling problems are minimized. The use of Ti overlying the Ir/TaN structure also helps prevent hillock formation during annealing. A method of forming a multilayer Ir conductive structure and Ir ferroelectric electrode are also provided.

    Method for forming an iridium oxide (IrOx) nanowire neural sensor array
    66.
    发明授权
    Method for forming an iridium oxide (IrOx) nanowire neural sensor array 有权
    形成氧化铱（IrOx）纳米线神经传感器阵列的方法

    公开(公告)号：US07905013B2

    公开(公告)日：2011-03-15

    申请号：US11809959

    申请日：2007-06-04

    申请人： Fengyan Zhang ,  Bruce D. Ulrich ,  Wei Gao ,  Sheng Teng Hsu

    发明人： Fengyan Zhang ,  Bruce D. Ulrich ,  Wei Gao ,  Sheng Teng Hsu

    IPC分类号： H01K3/10

    CPC分类号： A61N1/0543 ,  B82Y15/00 ,  B82Y30/00 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165 ,  Y10T29/49167 ,  Y10T29/49169 ,  Y10T428/24998

    摘要： An iridium oxide (IrOx) nanowire neural sensor array and associated fabrication method are provided. The method provides a substrate with a conductive layer overlying the substrate, and a dielectric layer overlying the conductive layer. The substrate can be a material such as Si, SiO2, quartz, glass, or polyimide, and the conductive layer is a material such as ITO, SnO2, ZnO, TiO2, doped ITO, doped SnO2, doped ZnO, doped TiO2, TiN, TaN, Au, Pt, or Ir. The dielectric layer is selectively wet etched, forming contact holes with sloped walls in the dielectric layer and exposing regions of the conductive layer. IrOx nanowire neural interfaces are grown from the exposed regions of the conductive layer. The IrOx nanowire neural interfaces each have a cross-section in a range of 0.5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval.

    摘要翻译： 提供氧化铱（IrOx）纳米线神经传感器阵列及相关制造方法。 该方法提供了具有覆盖在衬底上的导电层的衬底和覆盖导电层的电介质层。 基板可以是诸如Si，SiO 2，石英，玻璃或聚酰亚胺的材料，并且导电层是诸如ITO，SnO 2，ZnO，TiO 2，掺杂的ITO，掺杂的SnO 2，掺杂的ZnO，掺杂的TiO 2，TiN， TaN，Au，Pt或Ir。 电介质层被选择性地湿蚀刻，与电介质层中的倾斜壁形成接触孔并且暴露导电层的区域。 IrOx纳米线神经接口从导电层的暴露区域生长。 IrOx纳米线神经接口各自具有在0.5至10微米的范围内的横截面，并且可以被成形为圆形，矩形或椭圆形。

    IrOx Nanostructure Electrode Neural Interface Optical Device
    67.
    发明申请
    IrOx Nanostructure Electrode Neural Interface Optical Device 有权
    IrOx纳米结构电极神经界面光学器件

    公开(公告)号：US20090024182A1

    公开(公告)日：2009-01-22

    申请号：US12240501

    申请日：2008-09-29

    申请人： Fengyan Zhang ,  Sheng Teng Hsu

    发明人： Fengyan Zhang ,  Sheng Teng Hsu

    IPC分类号： A61N1/36

    CPC分类号： C30B25/00 ,  A61N1/0543 ,  B82Y5/00 ,  B82Y10/00 ,  B82Y30/00 ,  C30B29/16 ,  C30B29/605 ,  Y10S977/811 ,  Y10S977/904 ,  Y10S977/932

    摘要： An optical device with an iridium oxide (IrOx) electrode neural interface, and a corresponding fabrication method are provided. The method provides a substrate and forms a first conductive electrode overlying the substrate. A photovoltaic device having a first electrical interface is connected to the first electrode. A second electrical interface of the photovoltaic device is connected to a second conductive electrode formed overlying the photovoltaic device. An array of neural interface single-crystal IrOx nanostructures are formed overlying the second electrode, where x≦4. The IrOx nanostructures can be partially coated with an electrical insulator, such as SiO2, SiN, TiO2, or spin on glass (SOG), leaving the IrOx distal ends exposed. In one aspect, a buffer layer is formed overlying the second electrode surface, made from a material such as LiNbO3, LiTaO3, or SA, for the purpose of orienting the growth direction of the IrOx nanostructures.

    摘要翻译： 提供了具有氧化铱（IrOx）电极神经接口的光学器件及相应的制造方法。 该方法提供了一个衬底并且形成了覆盖衬底的第一导电电极。 具有第一电接口的光电器件连接到第一电极。 光电器件的第二电接口连接到形成在光伏器件上的第二导电电极。 形成了覆盖第二电极的神经界面单晶IrOx纳米结构阵列，其中x <= 4。 IrOx纳米结构可以部分地涂覆有电绝缘体，例如SiO 2，SiN，TiO 2或旋转玻璃（SOG），留下IrOx远端暴露。 在一个方面，为了定向IrOx纳米结构的生长方向，形成了由诸如LiNbO 3，LiTaO 3或SA的材料制成的第二电极表面上的缓冲层。

    One mask Pt/PCMO/Pt stack etching process for RRAM applications
    69.
    发明授权
    One mask Pt/PCMO/Pt stack etching process for RRAM applications 有权
    用于RRAM应用的一个掩模Pt / PCMO / Pt堆叠蚀刻工艺

    公开(公告)号：US07169637B2

    公开(公告)日：2007-01-30

    申请号：US10883228

    申请日：2004-07-01

    申请人： Fengyan Zhang ,  Lisa H. Stecker ,  Bruce D. Ulrich ,  Sheng Teng Hsu

    发明人： Fengyan Zhang ,  Lisa H. Stecker ,  Bruce D. Ulrich ,  Sheng Teng Hsu

    IPC分类号： H01L21/06 ,  H01L21/461

    CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675

    摘要： A one-mask etching method for use with a PCMO-containing RRAM to reduce stack side-wall residuals, includes preparing a substrate, taken from the group of substrates consisting of silicon, silicon dioxide and polysilicon; depositing a bottom electrode on the substrate; depositing a PCMO layer on the bottom electrode; depositing a top electrode on the PCMO layer; depositing a hard mask on the top electrode; depositing and patterning a photoresist layer on the hard mask; etching the hard mask; etching the top electrode using a first etching process having an etching atmosphere consisting of Ar, O2, and Cl2; etching the PCMO layer using an etching process taken from the group of etching processes consisting of the first etching process and a second etching process having an etching atmosphere consisting of Ar and O2. etching the bottom electrode using the first etching process; and completing the RRAM device.

    摘要翻译： 包含含PCMO的RRAM以减少堆叠侧壁残留物的单掩模蚀刻方法包括制备从由硅，二氧化硅和多晶硅组成的一组衬底取得的衬底; 在底物上沉积底部电极; 在底部电极上沉​​积PCMO层; 在PCMO层上沉积顶部电极; 在顶部电极上沉​​积硬掩模; 在硬掩模上沉积和图案化光致抗蚀剂层; 蚀刻硬掩模; 使用具有由Ar，O 2和Cl 2组成的蚀刻气氛的第一蚀刻工艺蚀刻顶部电极; 使用从由第一蚀刻工艺和由Ar和O 2组成的蚀刻气氛的第二蚀刻工艺组成的蚀刻工艺组中的蚀刻工艺来蚀刻PCMO层。 使用第一蚀刻工艺蚀刻底部电极; 并完成RRAM设备。

    Iridium oxide nanostructure
    70.
    发明授权
    Iridium oxide nanostructure 有权
    氧化铱纳米结构

    公开(公告)号：US07053403B1

    公开(公告)日：2006-05-30

    申请号：US11339876

    申请日：2006-01-26

    申请人： Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff ,  Sheng Teng Hsu

    发明人： Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff ,  Sheng Teng Hsu

    IPC分类号： H01L29/10 ,  H01L29/12

    CPC分类号： H01L21/31111 ,  B81C1/00111 ,  B82Y10/00

    摘要： A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas of the second region exposed by the non-continuous IrOx film; and, lifting off the IrOx nanostructures overlying the second region. Typically, the first region is formed from a first material and the second region from a second material, different than the first material. For example, the first material can be a refractory metal, or refractory metal oxide. The second material can be SiOx. The step of selectively etching areas of the second region exposed by the non-continuous IrOx film includes exposing the substrate to an etchant that is more reactive with the second material than the IrOx.

    摘要翻译： 提供了用于构图氧化铱（IrOx）纳米结构的方法。 该方法包括：在第二区域附近形成衬底第一区域; 从覆盖第一区域的连续IrOx膜生长IrOx纳米结构; 同时从覆盖第二区域的非连续IrOx膜生长IrOx纳米结构; 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域; 并提升覆盖第二区域的IrOx纳米结构。 通常，第一区域由第一材料形成，第二区域由不同于第一材料的第二材料形成。 例如，第一种材料可以是难熔金属或难熔金属氧化物。 第二种材料可以是SiOx。 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域的步骤包括将衬底暴露于与IrOx比第二材料更具反应性的蚀刻剂。