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120 条记录 (耗时 0.052 秒)

    Method of making multi-level wiring in a semiconductor device
    63.
    发明授权
    Method of making multi-level wiring in a semiconductor device 有权
    在半导体器件中制造多层布线的方法

    公开(公告)号：US06579785B2

    公开(公告)日：2003-06-17

    申请号：US09767724

    申请日：2001-01-24

    申请人： Hiroshi Toyoda ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Hideaki Hirabayashi

    发明人： Hiroshi Toyoda ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Hideaki Hirabayashi

    IPC分类号： H01L2144

    CPC分类号： H01L21/76849 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of manufacturing a semiconductor device, which comprises the steps of forming an intermediate layer on an insulating layer, forming a groove in the intermediate layer and the insulating layer, forming a first barrier layer on the intermediate layer, depositing a wiring layer on the first barrier layer to thereby fill the groove with the wiring layer, performing a flattening treatment of the wiring layer, removing a surface portion of the wiring to thereby permit the surface of the wiring to be recessed lower than a surface of the insulating layer, thus forming a recessed portion, forming a second barrier layer on the intermediate layer and on an inner wall of the recessed portion, performing a flattening treatment of the second barrier layer, thereby, and selectively removing the intermediate layer, exposing the insulating layer.

    摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在绝缘层上形成中间层，在中间层中形成沟槽和绝缘层，在中间层上形成第一阻挡层，在其上沉积布线层 第一阻挡层，从而使布线层填充沟槽，对布线层进行平坦化处理，去除布线的表面部分，从而允许布线的表面比绝缘层的表面凹陷，因此 形成凹部，在所述中间层和所述凹部的内壁上形成第二阻挡层，对所述第二阻挡层进行平坦化处理，从而选择性地除去所述中间层，使所述绝缘层露出。

    Method of manufacturing a semiconductor device
    65.
    发明授权
    Method of manufacturing a semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06518177B1

    公开(公告)日：2003-02-11

    申请号：US09783561

    申请日：2001-02-15

    申请人： Takashi Kawanoue ,  Junichi Wada ,  Tetsuo Matsuda ,  Hisashi Kaneko

    发明人： Takashi Kawanoue ,  Junichi Wada ,  Tetsuo Matsuda ,  Hisashi Kaneko

    IPC分类号： H01L214763

    CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/53209 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device is formed by a compound film &agr;&ggr;x made of at least one element &agr; selected from metal elements and at least one element &ggr; selected from the group consisting of boron, carbon, and nitrogen on a base layer containing oxygen (O), and forming a compound film &agr;&ggr;yOz by causing the compound film &agr;&ggr;x to reduce the base layer and thereby oxidizing the compound film &agr;&ggr;x on an interface of the compound film &agr;&ggr;x and the base layer, wherein each of x and y is a ratio of the number of atoms of the element &ggr; to the number of atoms of the element &agr;, and z is a ratio of the number of atoms of the oxygen to the number of atoms of the element &agr;.

    摘要翻译： 通过由选自金属元素的至少一种元素α和在含氧（O）的基底层上选自硼，碳和氮的至少一种元素γ制成的化合物膜，形成半导体器件，以及 通过使化合物膜alphagammax减少基底层从而氧化化合物膜的碱性和底层的界面上的化合物膜，形成化合物膜alphagammayOz，其中x和y分别为原子数 元素γ与元素α的原子数之比，z是氧原子数与元素α原子数之比。

    Film formation method
    67.
    发明授权
    Film formation method 有权
    成膜方法

    公开(公告)号：US06403481B1

    公开(公告)日：2002-06-11

    申请号：US09371221

    申请日：1999-08-10

    申请人： Tetsuo Matsuda ,  Hisashi Kaneko

    发明人： Tetsuo Matsuda ,  Hisashi Kaneko

    IPC分类号： H01L214763

    CPC分类号： H01L21/76858 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76886 ,  H01L2221/1089

    摘要： A film formation method for manufacture of a semiconductor device includes the steps of forming a first metal film as a continuous film on a substrate, forming a second metal film as discontinuous films on the substrate formed with the first metal film, and forming a third metal film by plating on the substrate formed with the first and second metal films.

    摘要翻译： 用于制造半导体器件的成膜方法包括以下步骤：在基板上形成作为连续膜的第一金属膜，在形成有第一金属膜的基板上形成作为不连续膜的第二金属膜，以及形成第三金属 通过在由第一和第二金属膜形成的基板上电镀。

    Method of manufacturing a copper interconnect
    68.
    发明授权
    Method of manufacturing a copper interconnect 失效
    制造铜互连的方法

    公开(公告)号：US06348402B1

    公开(公告)日：2002-02-19

    申请号：US09526880

    申请日：2000-03-16

    申请人： Takashi Kawanoue ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Tadashi Iijima

    发明人： Takashi Kawanoue ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Tadashi Iijima

    IPC分类号： H01L214763

    CPC分类号： H01L21/76846 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76888 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A groove or hole is formed in an insulating layer formed on a semiconductor substrate, and a first conductive layer including a first metal element is formed on a surface of the insulating layer. By oxidizing the first conductive layer, an oxide layer of the first metal element is formed on a surface of the first conductive layer. A second conductive layer including a second metal element having a free energy of oxide formation lower than that of the first metal element is deposited thereon. By reducing the oxide layer of the first metal element by the second metal element, an oxide layer of the second metal element is formed at the interface between the first conductive layer and the second conductive layer. Further, an interconnection is buried in the groove or hole of the insulating layer. Thereby, a thin second metal oxide layer having excellent barrier properties against an interconnection material and excellent adhesion to the interconnection material can be selectively formed with a uniform thickness on the surface of the first conductive layer used as a barrier metal layer of the interconnection.

    摘要翻译： 在形成于半导体衬底上的绝缘层中形成沟槽，在绝缘层的表面上形成包括第一金属元件的第一导电层。 通过氧化第一导电层，在第一导电层的表面上形成第一金属元素的氧化物层。 在其上沉积包括具有低于第一金属元素的自由能的氧化物形成的第二金属元素的第二导电层。 通过由第二金属元件还原第一金属元件的氧化物层，在第一导电层和第二导电层之间的界面处形成第二金属元素的氧化物层。 此外，互连被埋在绝缘层的凹槽或孔中。 由此，可以在用作互连的阻挡金属层的第一导电层的表面上选择性地形成具有优良的互连材料阻隔性和对互连材料的优异粘附性的薄的第二金属氧化物层。