公开(公告)号：US09905467B2

公开(公告)日：2018-02-27

申请号：US14971907

申请日：2015-12-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Sheng Li ,  Hsin-Chieh Huang ,  Chi-Wen Liu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/3115 ,  H01L21/311

CPC classification number: H01L21/823431 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0886 ,  H01L27/0924

Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.

公开(公告)号：US09837538B2

公开(公告)日：2017-12-05

申请号：US15214777

申请日：2016-07-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL CHIAO TUNG UNIVERSITY

Inventor： Chao-Hsin Chien ,  Chi-Wen Liu ,  Chen-Han Chou

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.

公开(公告)号：US20170345944A1

公开(公告)日：2017-11-30

申请号：US15169451

申请日：2016-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yen Lin ,  Chi-Wen Liu ,  Chong-Rong Wu ,  Xian-Rui Chang

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/78696 ,  H01L21/02568 ,  H01L21/0262 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/267 ,  H01L29/41766 ,  H01L29/66969 ,  H01L29/778 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78687

Abstract: The present disclosure provides a semiconductor device in accordance with some embodiments. The semiconductor device includes a first transition metal dichalcogenide film on a substrate; a second transition metal dichalcogenide film on the first transition metal dichalcogenide film; source and drain features formed over the second transition metal dichalcogenide film; and a first gate stack formed over the second transition metal dichalcogenide film and interposed between the source and drain feature.

公开(公告)号：US09773662B1

公开(公告)日：2017-09-26

申请号：US15173105

申请日：2016-06-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Miin-Jang Chen ,  Chi-Wen Liu ,  Po-Hsien Cheng

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/311 ,  H01L29/78 ,  H01L29/161 ,  H01L29/66

CPC classification number: H01L21/0228 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31116 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: In a method for fabricating a fine structure, a metal oxide layer is formed by using an atomic layer deposition over a substrate, and the metal oxide layer is removed. An interfacial oxide layer is formed between the metal oxide layer and the substrate. The interfacial oxide layer is an oxide of an element constituting the substrate, and the interfacial oxide layer is removed.

公开(公告)号：US20170110559A1

公开(公告)日：2017-04-20

申请号：US15392579

申请日：2016-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Cheng-Cheng Kuo ,  Chi-Wen Liu ,  Ming Zhu

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/324 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/265 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/66977 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/324 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/42392 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/7391 ,  H01L29/78618 ,  H01L29/78642

Abstract: A method for forming a tunneling field-effect transistor (TFET) is disclosed. The method includes etching a semiconductor substrate to form a semiconductor protrusion that protrudes out from a top surface of the semiconductor substrate, forming a drain region in lower portion of the semiconductor protrusion, and patterning a gate stack layer to form a gate stack. The gate stack has a gating surface that directly contacts and wraps around a middle portion of the semiconductor protrusion. The method further includes forming a source region in an upper portion of the semiconductor protrusion and forming a source contact over the source region, the source contact have a first width that is larger than a width of the source region.

公开(公告)号：US20150054039A1

公开(公告)日：2015-02-26

申请号：US13970790

申请日：2013-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Zhi-Chang Lin ,  Chao Hsiung Wang ,  Chi-Wen Liu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/76

CPC classification number: H01L29/785 ,  H01L21/76 ,  H01L21/76229 ,  H01L29/66795

Abstract: The present disclosure relates to a Fin field effect transistor (FinFET) device having epitaxial enhancement structures, and an associated method of fabrication. In some embodiments, the FinFET device has a semiconductor substrate having a plurality of isolation regions overlying the semiconductor substrate. A plurality of three-dimensional fins protrude from a top surface of the semiconductor substrate at locations between the plurality of isolation regions. Respective three-dimensional fins have an epitaxial enhancement structure that introduces a strain into the three-dimensional fin. The epitaxial enhancement structures are disposed over a semiconductor material within the three-dimensional fin at a position that is more than 10 nanometers above a bottom of an adjacent isolation region. Forming the epitaxial enhancement structure at such a position provides for sufficient structural support to avoid isolation region collapse.

Abstract translation: 本公开涉及具有外延增强结构的Fin场效应晶体管（FinFET）器件及其相关制造方法。 在一些实施例中，FinFET器件具有半导体衬底，其具有覆盖半导体衬底的多个隔离区域。 在多个隔离区域之间的位置处，多个三维翅片从半导体衬底的顶表面突出。 相应的三维翅片具有向三维翅片引入应变的外延增强结构。 外延增强结构被布置在三维鳍片内的半导体材料上方，位于相邻隔离区域的底部之上超过10纳米的位置。 在这样的位置形成外延增强结构提供足够的结构支撑以避免隔离区域崩溃。

公开(公告)号：US20250169135A1

公开(公告)日：2025-05-22

申请号：US19027055

申请日：2025-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ming Chang ,  Chi-Wen Liu ,  Cheng-Chien Li ,  Hsin-Chieh Huang

IPC: H10D62/60 ,  H01L21/02 ,  H01L21/265 ,  H10D30/01 ,  H10D30/62 ,  H10D30/69 ,  H10D62/10 ,  H10D62/834

Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.

公开(公告)号：US12068383B2

公开(公告)日：2024-08-20

申请号：US17813110

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Chi-Wen Liu ,  Ying-Keung Leung

IPC: H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H10B12/00

CPC classification number: H01L29/41791 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785 ,  H10B12/056 ,  H01L29/66545

Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.

公开(公告)号：US12034077B2

公开(公告)日：2024-07-09

申请号：US17663267

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Chi-Wen Liu ,  Ying-Keung Leung

IPC: H01L29/78 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/165

CPC classification number: H01L29/7856 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78696 ,  H01L29/165 ,  H01L2029/7858

Abstract: A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.

公开(公告)号：US11631768B2

公开(公告)日：2023-04-18

申请号：US16459511

申请日：2019-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Huang-Siang Lan ,  CheeWee Liu ,  Chi-Wen Liu ,  Shih-Hsien Huang ,  I-Hsieh Wong ,  Hung-Yu Yeh ,  Chung-En Tsai

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L27/092 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8238

Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm−3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.