公开(公告)号：US20100029075A1

公开(公告)日：2010-02-04

申请号：US12181359

申请日：2008-07-29

Applicant: Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

Inventor： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC: H01L21/4763

CPC classification number: H01L21/76898 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.

Abstract translation: 提出了通过晶片通孔（TWV）和标准触点在两个单独的工艺中形成以防止铜第一金属层挤压和短路的方法。 在一个实施例中，一种方法可以包括将TWV形成到衬底上并且在衬底上形成第一介电层; 在所述衬底和所述TWV上形成第二电介质层; 通过所述第二电介质层形成至少一个接触到所述TWV和与所述衬底上的其它结构的至少一个接触; 以及在所述第二电介质层上形成第一金属布线层，所述第一金属布线层与所述触点中的至少一个接触。

公开(公告)号：US20080290525A1

公开(公告)日：2008-11-27

申请号：US11751105

申请日：2007-05-21

Applicant: Brent A. Anderson ,  Paul S. Andry ,  Edmund J. Sprogis ,  Cornelia K. Tsang

Inventor： Brent A. Anderson ,  Paul S. Andry ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01L23/482 ,  H01L21/4763

CPC classification number: H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68368 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01019 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/19041 ,  H01L2924/19043

Abstract: A silicon-on-insulator (SOI) structure is provided for forming through vias in a silicon wafer carrier structure without backside lithography. The SOI structure includes the silicon wafer carrier structure bonded to a silicon substrate structure with a layer of buried oxide and a layer of nitride lo separating these silicon structures. Vias are formed in the silicon carrier structure and through the oxide layer to the nitride layer and the walls of the via are passivated. The vias are filled with a filler material of either polysilicon or a conductive material. The substrate structure is then etched back to the nitride layer and the nitride layer is etched back to the filler material. Where the filler material is polysilicon, the polysilicon is etched away forming an open via to the top surface of the carrier wafer structure. The via is then backfilled with conductive material.

Abstract translation: 提供绝缘体上硅（SOI）结构，用于在硅晶片载体结构中形成通孔，而无需背面光刻。 SOI结构包括与硅衬底结构结合的硅晶片载体结构，其具有掩埋氧化物层和分离这些硅结构的氮化物层。 在硅载体结构中形成通孔，并且通过氧化物层到达氮化物层，并且通孔的壁被钝化。 通孔填充有多晶硅或导电材料的填充材料。 然后将衬底结构回蚀刻到氮化物层，氮化物层被回蚀刻到填充材料上。 当填充材料是多晶硅时，多晶硅被蚀刻掉，形成开口通孔到载体晶片结构的顶表面。 然后通孔用导电材料回填。

公开(公告)号：US20080231311A1

公开(公告)日：2008-09-25

申请号：US12129040

申请日：2008-05-29

Applicant: VINCENZO CONDORELLI ,  Claudius Feger ,  Kevin C. Gotze ,  Nihad Hadzic ,  John U. Knickerbocker ,  Edmund J. Sprogis

Inventor： VINCENZO CONDORELLI ,  Claudius Feger ,  Kevin C. Gotze ,  Nihad Hadzic ,  John U. Knickerbocker ,  Edmund J. Sprogis

IPC: G01R31/26

CPC classification number: H01L23/576 ,  H01L23/5383 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/19103 ,  H01L2924/19107 ,  Y10T29/53039 ,  Y10T29/53052 ,  Y10T29/53178 ,  H01L2924/00

Abstract: A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.

Abstract translation: 提供了一种物理上安全的处理组件，其包括安装在基板上的模具，以便将模具的电触点夹在模具和基板之间。 衬底设置有电连接到管芯触点并延伸穿过衬底的衬底触点和导电路径。 电导体围绕导电路径。 监控电路检测一个或多个电导体的连续性的断裂，并且优选地使组件不可操作。 优选地，提供环氧树脂封装以防止探测工具能够到达管芯或衬底接触。

公开(公告)号：US20080206960A1

公开(公告)日：2008-08-28

申请号：US11679226

申请日：2007-02-27

Applicant: Bing Dang ,  Mario J. Interrante ,  John Knickerbocker ,  Edmund J. Sprogis

Inventor： Bing Dang ,  Mario J. Interrante ,  John Knickerbocker ,  Edmund J. Sprogis

IPC: H01L21/30

CPC classification number: G01R31/2898 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/98 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A method for removing a thinned silicon structure from a substrate, the method includes selecting the silicon structure with soldered connections for removal; applying a silicon structure removal device to the silicon structure and the substrate, wherein the silicon structure removal device comprises a pre-determined temperature setpoint for actuation within a range from about eighty percent of a melting point of the soldered connections to about the melting point; heating the silicon structure removal device and the soldered connections of the silicon structure to within the range to actuate the silicon structure removal device; and removing the thinned silicon structure. Also disclosed is a structure including a plurality of layers, at least one layer including a thinned silicon structure and solder coupling the layer to another layer of the plurality; wherein the solder for each layer has a predetermined melting point.

Abstract translation: 一种用于从衬底去除薄化硅结构的方法，所述方法包括用焊接连接选择硅结构以便去除; 将硅结构去除装置施加到所述硅结构和所述衬底，其中所述硅结构去除装置包括用于在所述焊接连接的熔点的约80％到约熔点范围内的致动的预定温度设定点; 将硅结构去除装置和硅结构的焊接连接加热到致动硅结构去除装置的范围内; 并去除薄的硅结构。 还公开了包括多个层的结构，至少一个层，包括薄化硅结构和将该层耦合到多个层中的另一层的焊料; 其中每层的焊料具有预定的熔点。

公开(公告)号：US20080182361A1

公开(公告)日：2008-07-31

申请号：US12056808

申请日：2008-03-27

Applicant: Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

Inventor： Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01L21/02

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5382 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

公开(公告)号：US07402442B2

公开(公告)日：2008-07-22

申请号：US11314272

申请日：2005-12-21

Applicant: Vincenzo Condorelli ,  Claudius Feger ,  Kevin C. Gotze ,  Nihad Hadzic ,  John U. Knickerbocker ,  Edmund J. Sprogis

Inventor： Vincenzo Condorelli ,  Claudius Feger ,  Kevin C. Gotze ,  Nihad Hadzic ,  John U. Knickerbocker ,  Edmund J. Sprogis

IPC: H01L23/58 ,  H01L21/00 ,  B23Q15/00

CPC classification number: H01L23/576 ,  H01L23/5383 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/19103 ,  H01L2924/19107 ,  Y10T29/53039 ,  Y10T29/53052 ,  Y10T29/53178 ,  H01L2924/00

Abstract: A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.

Abstract translation: 提供了一种物理上安全的处理组件，其包括安装在基板上的模具，以便将模具的电触点夹在模具和基板之间。 衬底设置有电连接到管芯触点并延伸穿过衬底的衬底触点和导电路径。 电导体围绕导电路径。 监视电路检测一个或多个电导体的连续性断裂，并且优选地使组件不可操作。 优选地，提供环氧树脂封装以防止探测工具能够到达管芯或衬底接触。

公开(公告)号：US07361989B1

公开(公告)日：2008-04-22

申请号：US11528227

申请日：2006-09-26

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC: H01L23/48

CPC classification number: H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Abstract translation: 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

公开(公告)号：US07310036B2

公开(公告)日：2007-12-18

申请号：US10905546

申请日：2005-01-10

Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Terence B. Hook ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Anthony K Stamper ,  William J. Murphy

Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Terence B. Hook ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Anthony K Stamper ,  William J. Murphy

IPC: H01C1/08

CPC classification number: H01C7/1013 ,  H01C1/084 ,  H01L2924/0002 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

Abstract: A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.

Abstract translation: 提供带散热片的电阻。 散热器包括具有导热性高的金属或其它热导体的导电路径。 为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。 因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。 除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

公开(公告)号：US06661100B1

公开(公告)日：2003-12-09

申请号：US10210631

申请日：2002-07-30

Applicant: Brent A. Anderson ,  Randolph F. Knarr ,  Sarah H. Knickerbocker ,  Edmund J. Sprogis ,  Kamalesh K. Srivastava

Inventor： Brent A. Anderson ,  Randolph F. Knarr ,  Sarah H. Knickerbocker ,  Edmund J. Sprogis ,  Kamalesh K. Srivastava

IPC: H01L2348

CPC classification number: H01L23/49816 ,  H01L23/13 ,  H01L23/5286 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011

Abstract: A low impedance power distribution structure and method for substrate packaging of semiconductor chips containing very large scale integrated circuit (VLSI) circuits, such as microprocessors and associated memory, is presented. The power distribution structure incorporates under bump metallurgy (UBM) solder bump forming technology to produce not only solder bump connections that are vertically oriented, but also low impedance distribution wires that are horizontally oriented, and which provide electrical interconnection between various selected electrical contact points, such as solder bumps. These low impedance distribution wires introduce the benefits of low characteristic impedance to the substrate's power distribution structure.

Abstract translation: 提出了一种用于包含诸如微处理器和相关存储器之类的大规模集成电路（VLSI）电路的半导体芯片的基板封装的低阻抗配电结构和方法。 功率分配结构包括凸块式冶金（UBM）焊料凸块形成技术，不仅产生垂直取向的焊料凸块连接，而且还产生水平定向的低阻抗分布导线，并且在各种选择的电接触点之间提供电互连， 如焊锡凸块。 这些低阻抗分布导线将低特性阻抗的优点引入衬底的配电结构。

公开(公告)号：US06213376B1

公开(公告)日：2001-04-10

申请号：US09098828

申请日：1998-06-17

Applicant: George C. Correia ,  John E. Cronin ,  Edmund J. Sprogis

Inventor： George C. Correia ,  John E. Cronin ,  Edmund J. Sprogis

IPC: B23K3704

CPC classification number: H01L21/6835 ,  B23K37/0408 ,  B23K2101/40 ,  H01L25/50 ,  H01L2221/68313 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2924/30105 ,  Y10T29/53978 ,  H01L2924/00014

Abstract: An apparatus used for holding a first semiconductor device in proper alignment to a second semiconductor device, whose size is different from the first device, while performing a C4 bond between the two devices. The apparatus for holding the two devices in proper alignment consists of a holding fixture, which includes upper and lower pocket receptacles for receiving the semiconductor devices. The semiconductor devices are placed into the respective upper and lower slots aligned to two or more edges of the holding fixture.

Abstract translation: 一种用于在与两个装置之间执行C4键的同时保持尺寸与第一装置不同的第二半导体装置正确对准的装置。 用于将两个装置保持正确对准的装置包括保持夹具，其包括用于接收半导体装置的上部和下部口袋容器。 将半导体器件放置在与保持夹具的两个或更多个边缘对准的相应的上部和下部狭缝中。