公开(公告)号：US20150284244A1

公开(公告)日：2015-10-08

申请号：US14676738

申请日：2015-04-01

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Yi-Ming CHANG

IPC: B81C1/00 ,  H01L21/683 ,  H01L23/00 ,  H01L27/146 ,  H01L21/78

CPC classification number: B81C1/00896 ,  B81B7/007 ,  B81B2207/096 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L24/11 ,  H01L24/43 ,  H01L24/83 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2224/0231 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/05032 ,  H01L2924/05432 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for forming a chip package is provided. The method includes providing a substrate and a capping layer, wherein the substrate has a sensing device therein adjacent to a surface of the substrate. The capping layer is attached to the surface of the substrate by an adhesive layer, wherein the adhesive layer covers the sensing device. A dicing process is performed on the substrate, the adhesive layer, and the capping layer along a direction to form individual chip packages.

Abstract translation: 提供了一种形成芯片封装的方法。 该方法包括提供衬底和覆盖层，其中衬底在其中邻近衬底的表面具有感测装置。 封盖层通过粘合剂层附接到基底的表面，其中粘合剂层覆盖感测装置。 沿着形成单个芯片封装的方向在衬底，粘合剂层和覆盖层上进行切割工艺。

公开(公告)号：US20150206916A1

公开(公告)日：2015-07-23

申请号：US14595870

申请日：2015-01-13

Applicant: XINTEC INC.

Inventor： Po-Han LEE ,  Shu-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO ,  Chien-Hung LIU

IPC: H01L27/146 ,  H01L31/0203

CPC classification number: H01L27/14632 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/1469 ,  H01L2224/11

Abstract: A manufacturing method of a semiconductor device includes the following steps. A temporary bonding layer is used to adhere a carrier to a first surface of a wafer. A redistribution layer, an insulating layer, and a conductive structure are formed on a second surface of the wafer opposite to the first surface, such that a semiconductor element is formed. The semiconductor element is diced from the insulating layer to the carrier, such that the semiconductor element forms at least one sub-semiconductor element. UV light is used to irradiate the sub-semiconductor element, such that adhesion of the temporary bonding layer is eliminated. The carrier of the sub-semiconductor element is removed.

Abstract translation: 半导体器件的制造方法包括以下步骤。 临时粘合层用于将载体粘附到晶片的第一表面。 在与第一表面相对的晶片的第二表面上形成再分布层，绝缘层和导电结构，从而形成半导体元件。 半导体元件从绝缘层切割到载体，使得半导体元件形成至少一个子半导体元件。 UV光用于照射次半导体元件，从而消除了临时粘合层的粘附。 子半导体元件的载体被去除。

公开(公告)号：US20140312478A1

公开(公告)日：2014-10-23

申请号：US14255883

申请日：2014-04-17

Applicant: XINTEC INC.

Inventor： Chia-Sheng LIN ,  Yen-Shih HO ,  Tsang-Yu LIU

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/49107 ,  H01L2224/494 ,  H01L2224/8536 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package is provided. The chip package comprises a semiconductor chip, an isolation layer, a redistributing metal layer, and a bonding pad. The semiconductor chip has a first conducting pad disposed on a lower surface, and a first hole corresponding to the first conducting pad. The first hole and the isolation layer extend from an upper surface to the lower surface to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has a redistributing metal line corresponding to the first conducting pad, the redistributing metal line is connected to the first conducting pad through the opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the first conducting pad to the bonding pad. A method thereof is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括半导体芯片，隔离层，再分布金属层和接合焊盘。 半导体芯片具有设置在下表面上的第一导电焊盘和对应于第一导电焊盘的第一孔。 第一孔和隔离层从上表面延伸到下表面以暴露第一导电垫。 再分布金属层设置在隔离层上并具有对应于第一导电焊盘的再分布金属线，再分布金属线通过开口连接到第一导电焊盘。 接合焊盘设置在隔离层和半导体芯片的一侧，其中再分布金属线延伸到接合焊盘以将第一导电焊盘电连接到接合焊盘。 还提供了其方法。

公开(公告)号：US20140264771A1

公开(公告)日：2014-09-18

申请号：US14290638

申请日：2014-05-29

Applicant: XINTEC INC.

Inventor： Hung-Jen LEE ,  Shu-Ming CHANG ,  Chen-Han CHIANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

Abstract: An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

Abstract translation: 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定在其上的多个预定划线的第一基板，其中，所述预定划线限定多个器件区域; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环和位于芯片支撑环的周边的切割支撑结构，并且间隔层具有 将切割支撑结构与芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一实施例提供一种芯片封装结构。

公开(公告)号：US20140154840A1

公开(公告)日：2014-06-05

申请号：US14173340

申请日：2014-02-05

Applicant: XINTEC INC.

Inventor： Shu-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L25/00

CPC classification number: H01L25/50 ,  B81C1/00238 ,  B81C2203/0785 ,  B81C2203/0792 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/10 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14517 ,  H01L2224/17517 ,  H01L2224/73103 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip; a hole extending from a surface of the first chip towards the second chip; a conducting layer disposed on the surface of the first chip and extending into the hole and electrically connected to a conducting region or a doped region in the first chip; and a support bulk disposed between the first chip and the second chip, wherein the support bulk substantially and/or completely covers a bottom of the hole.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：第一芯片; 设置在第一芯片上的第二芯片; 从所述第一芯片的表面向所述第二芯片延伸的孔; 导电层，设置在所述第一芯片的表面上并延伸到所述孔中并电连接到所述第一芯片中的导电区域或掺杂区域; 以及设置在所述第一芯片和所述第二芯片之间的支撑体，其中所述支撑体基本上和/或完全覆盖所述孔的底部。

公开(公告)号：US20140015111A1

公开(公告)日：2014-01-16

申请号：US13941854

申请日：2013-07-15

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Shih-Chin CHEN ,  Yi-Ming CHANG ,  Chien-Hui CHEN ,  Chia-Ming CHENG ,  Wei-Luen SUEN ,  Chen-Han CHIANG

IPC: H01L23/544 ,  H01L21/78

CPC classification number: H01L23/544 ,  H01L21/78 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2224/02371 ,  H01L2224/02377 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/06155 ,  H01L2224/0616 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/14155 ,  H01L2224/1416 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a device region disposed in the substrate; a dielectric layer located on the first surface of the semiconductor substrate; a plurality of conducting pads located in the dielectric layer and electrically connected to the device region; at least one alignment mark disposed in the semiconductor substrate and extending from the second surface towards the first surface.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和相对的第二表面的半导体衬底; 设置在所述基板中的装置区域; 位于半导体衬底的第一表面上的电介质层; 位于所述电介质层中并电连接到所述器件区域的多个导电焊盘; 设置在所述半导体衬底中并且从所述第二表面朝向所述第一表面延伸的至少一个对准标记。

公开(公告)号：US20130341747A1

公开(公告)日：2013-12-26

申请号：US13921999

申请日：2013-06-19

Applicant: XINTEC INC.

Inventor： Po-Shen LIN ,  Tsang-Yu LIU ,  Yen-Shih HO ,  Chih-Wei HO ,  Shih-Chin CHEN

IPC: H01L31/0232 ,  H01L31/02

CPC classification number: H01L31/0232 ,  H01L23/3114 ,  H01L27/14618 ,  H01L31/02 ,  H01L31/02327 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a chip including: a semiconductor substrate having a first surface; a device region formed in the semiconductor substrate; and a plurality of micro-lenses on the first surface and the device region; a cover substrate disposed on the chip, wherein the cover substrate is a transparent substrate; a spacer layer disposed between the chip and the cover substrate, wherein the spacer layer, the chip, and the cover substrate collectively surround a cavity in the device region; and at least one main lens on the cover substrate and in the cavity, wherein a width of the main lens is greater than that of each of the micro-lenses.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：芯片，包括：具有第一表面的半导体衬底; 形成在所述半导体衬底中的器件区域; 以及在所述第一表面和所述器件区域上的多个微透镜; 设置在所述芯片上的盖基板，其中所述盖基板为透明基板; 设置在所述芯片和所述覆盖基板之间的间隔层，其中所述间隔层，所述芯片和所述覆盖基板一起围绕所述器件区域中的空腔; 以及在所述盖基板上和所述空腔中的至少一个主透镜，其中所述主透镜的宽度大于每个所述微透镜的宽度。

公开(公告)号：US20130328147A1

公开(公告)日：2013-12-12

申请号：US13912792

申请日：2013-06-07

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Ying-Nan WEN ,  Tsang-Yu LIU

IPC: H01L31/02 ,  H01L31/0232

CPC classification number: H01L27/14687 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L31/02002 ,  H01L31/0232 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region disposed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure disposed in the dielectric layer and electrically connected to the device region, a carrier substrate disposed on the dielectric layer; and a conducting structure disposed in a bottom surface of the carrier substrate and electrically contacting with the conducting pad structure.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 设置在所述半导体衬底中的器件区域; 设置在所述半导体衬底的第一表面上的电介质层; 布置在所述电介质层中并电连接到所述器件区的导电焊盘结构，设置在所述电介质层上的载体衬底; 以及设置在所述载体基板的底表面中并与所述导电焊盘结构电接触的导电结构。