公开(公告)号：US09780073B2

公开(公告)日：2017-10-03

申请号：US14886190

申请日：2015-10-19

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Peter B. Gillingham

IPC: H05K1/11 ,  H01L25/065 ,  G11C5/02 ,  G11C5/06 ,  H01L23/48 ,  H01L23/544 ,  H01L21/02 ,  H01L21/82 ,  H03K17/00 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L25/0657 ,  G11C5/02 ,  G11C5/06 ,  H01L21/02697 ,  H01L21/82 ,  H01L23/481 ,  H01L23/5286 ,  H01L23/544 ,  H01L24/03 ,  H01L24/16 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/14 ,  H03K17/00 ,  H01L2924/00

Abstract: In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.

公开(公告)号：US09767881B2

公开(公告)日：2017-09-19

申请号：US15054873

申请日：2016-02-26

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Jin-Ki Kim ,  HakJune Oh

IPC: G11C7/00 ,  G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/40622

Abstract: A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

公开(公告)号：USRE46549E1

公开(公告)日：2017-09-12

申请号：US14025203

申请日：2013-09-12

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Eun-Young Minn ,  Young-Hoon Park ,  Chi-Hoon Lee ,  Hyo-Dong Ban

IPC: H01L23/544 ,  H01L23/26 ,  H01L23/31

CPC classification number: H01L23/26 ,  H01L23/3178 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

Abstract: An integrated circuit chip having an anti-moisture-absorption film at the edge thereof and a method of forming the anti-moisture-absorption film are provided. In the integrated circuit chip which has predetermined devices inside and whose uppermost layer is covered with a passivation film, a trench is formed by etching interlayer dielectric films to a predetermined depth along the perimeter of the integrated circuit chip to be adjacent to the edge of the integrated circuit chip and an anti-moisture-absorption film is formed to fill the trench or is formed on the sidewall of the trench to a predetermined thickness, in order to prevent moisture from seeping into the edge of the integrated circuit chip. Moisture is effectively prevented from seeping into the edge of the chip by forming the anti-moisture-absorption film at the edge of the chip using the conventional processes of manufacturing the integrated circuit chip without an additional process.

公开(公告)号：US09685536B2

公开(公告)日：2017-06-20

申请号：US13407855

申请日：2012-02-29

Applicant: Er-Xuan Ping ,  Jeffrey A. McKee

Inventor： Er-Xuan Ping ,  Jeffrey A. McKee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L27/108

CPC classification number: H01L29/66666 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28562 ,  H01L27/10873 ,  H01L27/10876 ,  H01L29/66628 ,  H01L29/66787 ,  H01L29/66893 ,  H01L29/7834 ,  H01L29/78642

Abstract: Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of mono crystalline silicon on the surface of a semi conductive substrate, and forming a thin film of insulative material over the epitaxial layer. A second epitaxial layer is selectively, grown on the exposed surface of the initial epitaxially grown crystal layer, and a thin insulative film is deposited over the second epitaxial layer. Additional epitaxial layers are added as desired to provide a vertical structure of a desired height comprising multiple layers of single silicon crystals, each epitaxial layer have insulated sidewalls, with the uppermost epitaxial layer also with an insulated top surface.

公开(公告)号：US09660616B2

公开(公告)日：2017-05-23

申请号：US14865905

申请日：2015-09-25

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Barry Alan Hoberman ,  Daniel L Hillman ,  Jon Shiell

IPC: G06F17/50 ,  G06F1/32 ,  H02J4/00 ,  H03K3/012

CPC classification number: H03K3/012 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  H01L2924/00 ,  H01L2924/0002 ,  H02J4/00 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20 ,  Y10T307/406 ,  Y10T307/414

Abstract: Systems and methods for managing power in an integrated circuit using power islands are disclosed. The integrated circuit includes a plurality of power islands where power consumption is independently controlled within each of the power islands. A power manager determines a target power level for one of the power islands. The power manager then determines an action to change a consumption power level of the one of the power islands to the target power level. The power manager performs the action to change the consumption power level of the one of the power islands to the target power level.

公开(公告)号：US20170117052A1

公开(公告)日：2017-04-27

申请号：US15401858

申请日：2017-01-09

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Jin-Ki KIM ,  Peter B. GILLINGHAM

IPC: G11C16/30 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/143 ,  G11C5/145 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage.The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

公开(公告)号：US09595336B2

公开(公告)日：2017-03-14

申请号：US14926484

申请日：2015-10-29

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Hyoung Seub Rhie

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/14

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/14

Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array with multiple vertical gate NAND memory cell strings formed in a different vertical layers over a substrate which share a common set of word lines, where different groupings of NAND memory cell strings formed between dedicated pairings of source line structures and bit line structures form separately erasable blocks which are addressed and erased by applying an erase voltage to the source line structure of the erase block being erased while applying a ground voltage to the other source line structures in the array and a high pass voltage to the bit line structures in the array.

Abstract translation: 三维集成电路非易失性存储器阵列包括具有多个垂直栅极NAND存储器单元串的存储器阵列，该多个垂直栅极NAND存储器单元串形成在共享一组公共字线的衬底上的不同垂直层中，其中形成了不同的NAND存储器单元串组 在源线结构和位线结构的专用配对之间形成单独的可擦除块，其通过向擦除块擦除块的源极线结构施加擦除电压来寻址和擦除，同时向阵列中的其它源极线结构施加接地电压 以及对阵列中的位线结构的高通电压。

公开(公告)号：US09570123B2

公开(公告)日：2017-02-14

申请号：US14531432

申请日：2014-11-03

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Jin-Ki Kim

IPC: G11C7/10 ,  G11C5/02 ,  G11C7/12 ,  G11C16/24 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0679 ,  G11C5/025 ,  G11C7/1006 ,  G11C7/1033 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/12 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/107 ,  G11C2216/14 ,  G11C2216/20 ,  G11C2216/30

Abstract: A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.

Abstract translation: 一种具有串行数据接口和串行数据路径核心的存储器系统，用于从至少一个存储器组接收数据并将数据作为串行比特流提供给至少一个存储体。 记忆库分为两半，每半部分分为上下扇区。 每个扇区使用集成的自列解码电路并行提供与共享的二维页面缓冲器的数据。 存储器中的串行到并行数据转换器将并行数据从一半耦合到串行数据路径核心。 具有集成自列解码电路的共享二维页面缓冲器使每个存储体的电路和芯片面积开销最小化，并且串行数据通道内核减少了通常用于布线宽数据总线的芯片面积。 因此，与具有相同密度的单个存储体系统相比，实现多存储体系统而没有显着相应的芯片面积增加。

公开(公告)号：US09524783B2

公开(公告)日：2016-12-20

申请号：US14984303

申请日：2015-12-30

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Hakjune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G11C7/00 ,  G11C16/10 ,  G11C7/10 ,  G11C16/26 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Abstract translation: 公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

公开(公告)号：US20160277027A1

公开(公告)日：2016-09-22

申请号：US15079085

申请日：2016-03-24

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Bruce MILLAR

IPC: H03K19/00 ,  G11C11/4093 ,  H03H17/00

CPC classification number: H03K19/0005 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/4093 ,  G11C2207/2254 ,  H03H7/38 ,  H03H17/0045 ,  H04L25/0278 ,  H04L25/028

Abstract: A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.