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    Transistor employing vertically stacked self-aligned carbon nanotubes
    61.
    发明授权
    Transistor employing vertically stacked self-aligned carbon nanotubes 有权
    晶体管采用垂直堆叠的自对准碳纳米管

    公开(公告)号：US08895371B2

    公开(公告)日：2014-11-25

    申请号：US13605238

    申请日：2012-09-06

    Applicant: Qing Cao ,  Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

    Inventor： Qing Cao ,  Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

    IPC: H01L21/335 ,  H01L51/05 ,  H01L29/775 ,  H01L29/66 ,  H01L51/00 ,  H01L29/12 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/78

    CPC classification number: H01L51/057 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/125 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7827 ,  H01L51/0045 ,  H01L51/0048 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

    Abstract: A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel.

    Abstract translation: 形成包括具有第一等电点的第一等电点材料层和具有小于第一等电点的第二等电点的第二等电子材料层的垂直交替堆叠的鳍结构。 第一和第二等电点材料层在具有第一和第二等电点之间的pH的溶液中相反地充电。 通过阴离子表面活性剂将负电荷赋予碳纳米管。 静电引力使得碳纳米管选择性地附着在第一等电点材料层的表面上。 碳纳米管沿翅片结构的水平长度方向自对准地附接到第一等电点材料层。 可以形成晶体管，其采用多个垂直排列的水平碳纳米管作为沟道。

    QUANTUM DOT AND NANOWIRE SYNTHESIS
    62.
    发明申请
    QUANTUM DOT AND NANOWIRE SYNTHESIS 审中-公开
    量子和纳米合成

    公开(公告)号：US20140027710A1

    公开(公告)日：2014-01-30

    申请号：US13991134

    申请日：2011-12-03

    Applicant: Feng Liu ,  Gerald Stringfellow ,  Xiaobin Niu

    Inventor： Feng Liu ,  Gerald Stringfellow ,  Xiaobin Niu

    IPC: H01L21/02 ,  H01L33/06 ,  H01L29/12

    CPC classification number: H01L21/02601 ,  B82Y10/00 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/0259 ,  H01L21/02603 ,  H01L21/02636 ,  H01L29/0665 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/127 ,  H01L29/2003 ,  H01L33/007 ,  H01L33/06 ,  H01L33/18

    Abstract: A self-assembled semiconductor nanostructure includes a core and a shell, wherein one of the core or the shell is rich in a strained component and the other of the core or the shell is rich in an unstrained component, wherein the nanostructure is a quantum dot or a nanowire. A method includes growing a semiconductor alloy structure on a substrate using a growth mode that produces a semiconductor alloy structure having a self-assembled core and shell and allowing the structure to equilibrate such that one of the core or the shell is strained and the other is unstrained. Another method includes growing at least one semiconductor alloy nanostructures on a substrate, wherein the nanostructure comprises a strained component and an unstrained component, and controlling a compositional profile during said growing such that a transition between the strained component and an unstrained component is substantially continuous.

    Abstract translation: 自组装半导体纳米结构包括核和壳，其中核或壳中的一个富含应变组分，并且核或壳中的另一个富含未应变成分，其中纳米结构是量子点 或纳米线。 一种方法包括使用产生具有自组装芯和壳的半导体合金结构的生长模式在衬底上生长半导体合金结构，并允许结构平衡使得芯或壳中的一个被应变，而另一个是 无限制 另一种方法包括在衬底上生长至少一种半导体合金纳米结构，其中纳米结构包括应变组分和未应变组分，并且在所述生长期间控制组成分布，使得应变组分与未应变组分之间的过渡基本连续。

    Two-terminal resistance switching device and semiconductor device
    64.
    发明授权
    Two-terminal resistance switching device and semiconductor device 有权
    两端电阻开关器件和半导体器件

    公开(公告)号：US08604458B2

    公开(公告)日：2013-12-10

    申请号：US12671145

    申请日：2008-07-23

    Applicant: Hiroshi Suga ,  Yasuhisa Naitou ,  Masayo Horikawa ,  Tetsuo Shimizu

    Inventor： Hiroshi Suga ,  Yasuhisa Naitou ,  Masayo Horikawa ,  Tetsuo Shimizu

    IPC: H01L29/06

    CPC classification number: H01L29/125 ,  B82Y10/00 ,  B82Y30/00 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1253 ,  H01L51/0048 ,  H01L51/0591

    Abstract: The present invention is contemplated for providing a resistance switching device having a very small device size of approximately 20 nm×20 nm in its entirety, by taking advantage of a small diameter of a multilayered carbon nanotube or a multilayered carbon nanofiber per se, via a simpler manner that does not require any molecule inclusion step, with an excellent electric conductivity. Provided is a two-terminal resistance switching device, which has multilayered carbon nanofibers or multilayered carbon nanotubes disposed with a nano-scale gap width therebetween.

    Abstract translation: 本发明考虑用于通过利用多层碳纳米管或多层碳纳米纤维本身的小直径，通过经由一个或多个多层碳纳米纤维本身的优点，提供具有大约20nm×20nm的非常小的器件尺寸的电阻开关器件 更简单的方式，其不需要任何分子包合步骤，具有优异的导电性。 提供一种双端子电阻切换装置，其具有多层碳纳米纤维或多层碳纳米管，纳米尺度间隙宽度设置在其间。

    Semiconductor power switch having nanowires
    66.
    发明授权
    Semiconductor power switch having nanowires 有权
    具有纳米线的半导体功率开关

    公开(公告)号：US08319259B2

    公开(公告)日：2012-11-27

    申请号：US10587062

    申请日：2005-01-19

    Applicant: Franz Kreupl ,  Robert Seidel

    Inventor： Franz Kreupl ,  Robert Seidel

    IPC: H01L29/76

    CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/66439 ,  H01L51/0048 ,  H01L51/0541 ,  H01L51/0545

    Abstract: A semiconductor power switch and method is disclosed. In one Embodiment, the semiconductor power switch has a source contact, a drain contact, a semiconductor structure which is provided between the source contact and the drain contact, and a gate which can be used to control a current flow through the semiconductor structure between the source contact and the drain contact. The semiconductor structure has a plurality of nanowires which are connected in parallel and are arranged in such a manner that each nanowire forms an electrical connection between the source contact and the drain contact.

    Abstract translation: 公开了一种半导体功率开关和方法。 在一个实施例中，半导体功率开关具有源极接触，漏极接触，设置在源极接触和漏极接触之间的半导体结构，以及可用于控制通过半导体结构的电流 源极接触和漏极接触。 半导体结构具有并联连接的多个纳米线，并且以使得每个纳米线在源极触点和漏极触点之间形成电连接的方式布置。

    Rounded three-dimensional germanium active channel for transistors and sensors
    70.
    发明授权
    Rounded three-dimensional germanium active channel for transistors and sensors 失效
    用于晶体管和传感器的圆形三维锗活性通道

    公开(公告)号：US08101473B2

    公开(公告)日：2012-01-24

    申请号：US12501259

    申请日：2009-07-10

    Applicant: Hans Cho ,  Theodore I Kamins ,  Nathaniel Quitoriano

    Inventor： Hans Cho ,  Theodore I Kamins ,  Nathaniel Quitoriano

    IPC: H01L21/00 ,  H01L21/84

    CPC classification number: H01L29/423 ,  B82Y10/00 ,  G01N27/414 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/02667 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/125 ,  H01L29/205 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7854

    Abstract: A process is provided for fabricating rounded three-dimensional germanium active channels for transistors and sensors. For forming sensors, the process comprises providing a crystalline silicon substrate; depositing an oxide mask on the crystalline silicon substrate; patterning the oxide mask with trenches to expose linear regions of the silicon substrate; epitaxially grow germanium selectively in the trenches, seeded from the silicon wafer; optionally etching the SiO2 mask partially, so that the cross section resembles a trapezoid on a stem; and annealing at an elevated temperature. The annealing process forms the rounded channel. For forming transistors, the process further comprises depositing and patterning a gate oxide and gate electrode onto this structure to form the gate stack of a MOSFET device; and after patterning the gate, implanting dopants into the source and drain located on the parts of the germanium cylinder on either side of the gate line.

    Abstract translation: 提供了一种用于制造用于晶体管和传感器的圆形三维锗活性通道的工艺。 对于形成传感器，该方法包括提供晶体硅衬底; 在所述晶体硅衬底上沉积氧化物掩模; 用沟槽图案化氧化物掩模以暴露硅衬底的线性区域; 在沟槽中选择性地外延生长锗，从硅晶片接种; 可选地部分地蚀刻SiO 2掩模，使得横截面类似于杆上的梯形; 并在高温退火。 退火过程形成圆形通道。 为了形成晶体管，该工艺还包括将栅极氧化物和栅电极沉积并图案化到该结构上以形成MOSFET器件的栅叠层; 并且在图案化栅极之后，将掺杂剂注入位于栅极线两侧的锗圆筒部分上的源极和漏极。

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