公开(公告)号：US20170179382A1

公开(公告)日：2017-06-22

申请号：US15374957

申请日：2016-12-09

申请人： Microsemi SoC Corporation

发明人： John L. McCollum ,  Fethi Dhaoui ,  Frank W. Hawley

IPC分类号： H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC分类号： H01L45/085 ,  G11C13/0011 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/11 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/54 ,  G11C2213/56 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1675

摘要： A resistive random access memory device is formed in an integrated circuit between a first metal layer and a second metal layer and includes a first barrier layer disposed over the first metal layer, a tunneling dielectric layer disposed over the first barrier layer, a solid electrolyte layer disposed over the tunneling dielectric layer, an ion source layer disposed over the solid electrolyte layer, and a second barrier layer disposed over the ion source layer.

公开(公告)号：US09673389B2

公开(公告)日：2017-06-06

申请号：US13357149

申请日：2012-01-24

申请人： Kenichi Murooka

发明人： Kenichi Murooka

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L27/249 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/16

摘要： According to one embodiment, a memory device includes a first interconnect group, a second interconnect group, and a memory cell. In the first interconnect group, first interconnects are stacked. The first interconnect group includes first regions in which the first interconnects are formed along a first direction, and a second region in which first contact plugs are formed on the first interconnects. In the second region, the first interconnect group includes a step portion. Heights of adjacent terraces of the step portion are different from each other by the two or more first interconnects.

公开(公告)号：US09673256B2

公开(公告)日：2017-06-06

申请号：US15063179

申请日：2016-03-07

申请人： Micron Technology, Inc.

发明人： Yongjun Jeff Hu ,  Tsz W. Chan ,  Swapnil Lengade ,  Everett Allen McTeer ,  Shu Qin

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L27/2481 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/165 ,  H01L45/1675

摘要： Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner.

公开(公告)号：US20170155044A1

公开(公告)日：2017-06-01

申请号：US15229449

申请日：2016-08-05

申请人： KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

发明人： Jong Hyuk PARK ,  Sang-Soo LEE ,  Heesuk KIM ,  Jeong Gon SON ,  Wan Ki BAE ,  Keun-Young SHIN ,  Young Jin KIM

IPC分类号： H01L45/00

CPC分类号： H01L45/16 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625

摘要： Disclosed are nonvolatile resistance random access memory device and a fabrication method thereof. The nonvolatile resistance random access memory device includes a lower electrode, an insulator film formed on a surface of the lower electrode, and an upper electrode formed over the insulator film, the lower electrode includes a base, and a thin metal layer formed on a surface of the base, and the lower electrode has a 3D structural pattern in which a plurality of protruding structures is repeatedly arranged at a constant interval. The 3D metal structures have a shape selected from among a pyramid (quadrangular pyramid), a trapezoidal pyramid (pyramid with a flat top), a pillar, and a prism. Uniform conductive filaments are formed via the space between the 3D metal structures, whereby the nonvolatile resistance random access memory device is capable of being driven at a low operating voltage and has long-term stability.

公开(公告)号：US20170154925A1

公开(公告)日：2017-06-01

申请号：US15430888

申请日：2017-02-13

申请人： SanDisk Technologies LLC

发明人： Seiji Shimabukuro ,  Teruyuki Mine ,  Hiroyuki Ogawa ,  Naoki Takeguchi

IPC分类号： H01L27/24 ,  G11C13/00 ,  H01L45/00

CPC分类号： H01L27/249 ,  G11C5/025 ,  G11C7/18 ,  G11C8/12 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/025 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/35 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/148 ,  H01L45/149 ,  H01L45/16 ,  H01L45/1675

摘要： A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.

公开(公告)号：US20170154845A1

公开(公告)日：2017-06-01

申请号：US15430965

申请日：2017-02-13

申请人： SANDISK TECHNOLOGIES LLC

发明人： Seje Takaki

IPC分类号： H01L23/528 ,  H01L21/311 ,  G11C5/06 ,  H01L27/11582 ,  H01L27/11556 ,  G11C5/02 ,  H01L21/768 ,  H01L27/24

CPC分类号： H01L23/528 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C16/08 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/76877 ,  H01L21/76895 ,  H01L27/1052 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/122 ,  H01L45/16

摘要： A 3D nonvolatile memory has memory elements arranged in a three-dimensional pattern with a plurality of memory layers stacked over a semiconductor substrate. It has a 2D array of vertical bit lines and a plurality of staircase word lines. Each staircase word line has a series of alternating segments and risers and traverses the plurality of memory layers with a segment in each memory layer. The plurality of staircase word lines have their segments lined up to form a 2D array of stacks of segments. Riser for a pair of segments from each adjacent stacks at different memory layers is provided by a conductive sidewall layer of a stairwell disposed between the adjacent stacks. Multiple insulated conductive sidewall layers provide multiple risers for the adjacent stacks. Layer-by-layer stairwell excavation and sidewall processes between adjacent stacks create risers for different pairs of segments between stacks to form the staircase word lines.

公开(公告)号：US09666801B2

公开(公告)日：2017-05-30

申请号：US15156105

申请日：2016-05-16

申请人： Micron Technology, Inc.

发明人： Nishant Sinha ,  John Smythe ,  Bhaskar Srinivasan ,  Gurtej S. Sandhu ,  Joseph Neil Greeley ,  Kunal R. Parekh

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/1683 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.

公开(公告)号：US20170117325A1

公开(公告)日：2017-04-27

申请号：US15141072

申请日：2016-04-28

申请人： SK hynix Inc.

发明人： Jong-Gi KIM ,  Beom-Yong KIM ,  Kee-Jeung LEE

IPC分类号： H01L27/24 ,  G06F3/06 ,  H01L45/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

CPC分类号： H01L27/2409 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  H01L27/11507 ,  H01L27/1159 ,  H01L27/224 ,  H01L27/249 ,  H01L43/02 ,  H01L43/08 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: interlayer insulating layers and conductive first base layer patterns that are alternatively stacked over a substrate; a dielectric second base layer pattern that is in contact with sidewalls of the interlayer insulating layers; first electrodes that are in contact with sidewalls of the first base layer patterns; a second electrode disposed over outer sidewalls of the first electrodes; and a variable resistance layer pattern interposed between the first electrodes and the second electrode. Each of the first electrodes comprises an alloy that includes first and second elements. The first element is included in the first base layer patterns and the second element is included in the second base layer pattern.

公开(公告)号：US09634249B2

公开(公告)日：2017-04-25

申请号：US15207979

申请日：2016-07-12

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/1608 ,  H01L27/2436 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/16 ,  H01L45/1675 ,  H01L45/1691

摘要： A device includes a pillar-shaped insulating layer above a first pillar-shaped semiconductor layer. A resistance-changing film is around an upper portion of the pillar-shaped insulating layer and a lower electrode is around a lower portion of the pillar-shaped insulating layer and connected to the resistance-changing film. A reset gate insulating film surrounds the resistance-changing film, and a reset gate surrounds the reset gate insulating film.

公开(公告)号：US20170104156A1

公开(公告)日：2017-04-13

申请号：US15383105

申请日：2016-12-19

申请人： Micron Technology, Inc.

发明人： Jun Liu ,  Michael P. Violette

IPC分类号： H01L45/00

CPC分类号： H01L45/1273 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1675

摘要： Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.