公开(公告)号：US20180034505A1

公开(公告)日：2018-02-01

申请号：US15436826

申请日：2017-02-19

Applicant: STMicroelectronics SA

Inventor： Sebastien Dedieu ,  Marc Houdebine

IPC: H04B5/00 ,  G06K7/10 ,  H03L7/081 ,  H03L7/099 ,  H03L7/093

CPC classification number: H04B5/0031 ,  G06K7/10297 ,  H03L7/08 ,  H03L7/081 ,  H03L7/093 ,  H03L7/099 ,  H03L7/14 ,  H03L7/23 ,  H04B5/0056 ,  H04B5/0062 ,  H04B5/0093 ,  H04W4/80

Abstract: A method can be used for contactless communication of an object with a reader using active load modulation. A main clock signal is generated within the object. The generating includes a calibration phase and a transmission phase. The calibration phase includes locking an output signal of a controlled main oscillator onto a phase and frequency of a secondary clock signal received from the reader and estimating a frequency ratio between a frequency of the output signal of the main oscillator and a reference frequency of a reference signal originating from a reference oscillator. The transmission phase includes only frequency-locking the output signal of the main oscillator onto the frequency of the reference signal corrected by the estimated frequency ratio.

公开(公告)号：US09882034B2

公开(公告)日：2018-01-30

申请号：US15221051

申请日：2016-07-27

Applicant: STMicroelectronics SA

Inventor： Pascal Chevalier

IPC: H01L29/732 ,  H01L21/308 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L29/732 ,  H01L21/308 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7371

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening having sidewalls lined with an insulating sheath. A portion of the insulating sheath adjacent the base region is removed and a base contact region is formed by epitaxial material grown from a portion of the base region exposed by removal of the portion of the insulating sheath.

公开(公告)号：US20180014006A1

公开(公告)日：2018-01-11

申请号：US15204185

申请日：2016-07-07

Applicant: STMICROELECTRONICS SA

Inventor： Olivier POTHIER ,  Arnaud Bourge

IPC: H04N13/02 ,  H04N5/374 ,  H04N5/33 ,  H04N5/378 ,  G06T3/40

CPC classification number: H04N13/271 ,  G06T3/40

Abstract: An electronic device includes a SPAD array and readout circuitry coupled thereto. The readout circuitry generates a depth map having a first resolution, and a signal count map having a second resolution greater than the first resolution. The depth map corresponds to distance observations to an object. The signal count map corresponds to intensity observation sets of the object, with each intensity observation set including intensity observations corresponding to a respective distance observation in the depth map. An upscaling processor is coupled to the readout circuitry to calculate upscaling factors for each intensity observation set so that each distance observation has respective upscaling factors associated therewith. The depth map is then upscaled from the first resolution to the second resolution based on the respective upscaling factors.

公开(公告)号：US20170358459A1

公开(公告)日：2017-12-14

申请号：US15523742

申请日：2015-11-09

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA

Inventor： Shay REBOH ,  Laurent GRENOUILLET ,  Yves MORAND

IPC: H01L21/308 ,  H01L21/311 ,  H01L27/12

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/31144 ,  H01L27/1203

Abstract: A method for producing at least one pattern in a layer resting on a substrate, including: a) making amorphous at least one first block of an upper layer of crystalline material resting on a first amorphous supporting layer, while the crystalline structure of a second block of the upper layer that adjoins and is juxtaposed with the first block is preserved; b) partially recrystallizing the first block by using at least one side surface of the second block that is in contact with the first block as an area for the start of a recrystallization front, the partial recrystallization being carried out to preserve a region of amorphous material in the first block; c) selectively etching the amorphous material of the upper layer with respect to the crystalline material of the upper layer to form at least one first pattern in the upper layer.

公开(公告)号：US20170346443A1

公开(公告)日：2017-11-30

申请号：US15358350

申请日：2016-11-22

Applicant: STMicroelectronics SA

Inventor： Emmanuel Chataigner

IPC: H03B5/12

CPC classification number: H03B5/1231 ,  H03B5/1215 ,  H03B5/1253 ,  H03B5/1296 ,  H03B2200/0076

Abstract: An integrated circuit includes at least two identical, synchronous and independent oscillator circuits that are coupled one to one in parallel with each other at homologous oscillating nodes of the respective oscillator circuits. The coupling in parallel is made using at least one coupling track that is configured so as to not introduce any phase shift or to introduce a very small phase shift.

公开(公告)号：US09831288B2

公开(公告)日：2017-11-28

申请号：US15387850

申请日：2016-12-22

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives ,  STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA

Inventor： Laurent Grenouillet ,  Sotirios Athanasiou ,  Philippe Galy

IPC: H01L27/24 ,  G11C13/00 ,  H01L27/12 ,  H01L45/00 ,  H01L27/10

CPC classification number: H01L27/2454 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/53 ,  H01L27/101 ,  H01L27/1207 ,  H01L27/2436 ,  H01L28/00 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/147

Abstract: The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising: first and second conduction electrodes (201, 202); a channel zone (203) arranged between the first and second conduction electrodes; a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222); an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.

公开(公告)号：US20170329941A1

公开(公告)日：2017-11-16

申请号：US15390850

申请日：2016-12-27

Applicant: STMicroelectronics SA

Inventor： Jocelyn Leheup ,  Herve Sibert

IPC: G06F21/16 ,  H04L29/06 ,  G06F21/44 ,  G06F21/57

CPC classification number: G06F21/16 ,  G06F21/10 ,  G06F21/44 ,  G06F21/57 ,  G06F21/84 ,  G06F2221/034 ,  G06F2221/0733 ,  G06F2221/2105 ,  H04L63/1441 ,  H04N21/43635 ,  H04N21/4367

Abstract: A signal is protected against an attack by an enhancement process that checks the conformity of an actual state of the signal with respect to an expected state. A protective action is exercised on the signal if the actual state of the signal is not in conformity with the expected state, so as to neutralize or nullify said attack.

公开(公告)号：US09818646B2

公开(公告)日：2017-11-14

申请号：US15583342

申请日：2017-05-01

Applicant: STMicroelectronics SA

Inventor： Sylvain Joblot ,  Pierre Bar

IPC: G02B6/12 ,  H01L21/768 ,  H01L21/48 ,  H01L21/762 ,  H01L23/66 ,  H01P11/00

CPC classification number: H01L21/76831 ,  G02B6/12 ,  H01L21/4846 ,  H01L21/76224 ,  H01L21/76898 ,  H01L23/66 ,  H01P11/003

Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.

公开(公告)号：US09812615B2

公开(公告)日：2017-11-07

申请号：US14659751

申请日：2015-03-17

Applicant: STMicroelectronics SA ,  Commissariat a l'Energie Atomique et aux Energies Alternatives

Inventor： Laurent Frey ,  Michel Marty

IPC: H01L31/0232 ,  H01L27/146 ,  H01L33/00 ,  H01L21/66 ,  H01L33/44 ,  H01L31/0216 ,  G02B1/11 ,  H01L33/34 ,  H01L33/62

CPC classification number: H01L33/44 ,  G02B1/11 ,  G02B1/113 ,  H01L22/26 ,  H01L27/1462 ,  H01L27/14649 ,  H01L27/14669 ,  H01L31/02161 ,  H01L31/02165 ,  H01L33/0054 ,  H01L33/34 ,  H01L33/62 ,  H01L2933/0025 ,  H01L2933/0066

Abstract: A photodiode has an active portion formed in a silicon substrate and covered with a stack of insulating layers successively including at least one first silicon oxide layer, an antireflection layer, and a second silicon oxide layer. The quantum efficiency of the photodiode is optimized by: determining, for the infrared wavelength, first thicknesses of the second layer corresponding to maximum absorptions of the photodiode, and selecting, from among the first thicknesses, a desired thickness, eoxD, so that a maximum manufacturing dispersion is smaller than a half of a pseudo-period separating two successive maximum absorption values.

公开(公告)号：US09791346B1

公开(公告)日：2017-10-17

申请号：US15133614

申请日：2016-04-20

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Francois Carpentier ,  Patrick Lemaitre ,  Jean-Robert Manouvrier ,  Charles Baudot ,  Bertrand Borot

IPC: G01B9/00 ,  G01M11/02 ,  G02B6/28 ,  G02B6/34 ,  G02B6/12

CPC classification number: G01M11/02 ,  G01R31/2656 ,  G01R31/27 ,  G01R31/2884 ,  G01R31/303 ,  G01R31/311 ,  G01R31/31728 ,  G01R35/00 ,  G02B6/00 ,  G02B6/12004 ,  G02B6/2808 ,  G02B6/34

Abstract: A semiconductor device may include a semiconductor wafer, and a reference circuit carried by the semiconductor wafer. The reference circuit may include optical DUTs, a first set of photodetectors coupled to outputs of the optical DUTs, an optical splitter coupled to inputs of the optical DUTs, and a second set of photodetectors coupled to the optical splitter. The optical splitter is to be coupled to an optical source and configured to transmit a reference optical signal to the first set of photodetectors via the optical DUTs and the second set of photodetectors.