公开(公告)号：US08471362B2

公开(公告)日：2013-06-25

申请号：US13080042

申请日：2011-04-05

Applicant: Jong-joo Lee

Inventor： Jong-joo Lee

IPC: H01L21/02

CPC classification number: H01L27/0688 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1084 ,  G11C7/1096 ,  G11C8/06 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A three-dimensional (3D) semiconductor device including a plurality of stacked layers and a through-silicon via (TSV) electrically connecting the plurality of layers, in which in signal transmission among the plurality of layers, the TSV transmits a signal that swings in a range from an offset voltage that is higher than a ground voltage to a power voltage, thereby minimizing an influence of a metal-oxide-semiconductor (MOS) capacitance of TSV.

Abstract translation: 包括多个堆叠层的三维（3D）半导体器件和电连接多个层的贯穿硅通孔（TSV），其中在多个层之间的信号传输中，TSV发送摆动的信号 从高于接地电压的偏移电压到电源电压的范围，从而最小化TSV的金属氧化物半导体（MOS）电容的影响。

公开(公告)号：US08446016B2

公开(公告)日：2013-05-21

申请号：US13224670

申请日：2011-09-02

Applicant: Sun-Won Kang ,  Seung-Duk Baek ,  Jong-Joo Lee

Inventor： Sun-Won Kang ,  Seung-Duk Baek ,  Jong-Joo Lee

IPC: H01L23/538

CPC classification number: H01L25/0657 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311

Abstract: A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.

Abstract translation: 芯片堆叠包括通过使用粘合剂层作为中间介质堆叠的多个芯片，以及通过芯片形成的通孔电极以电耦合芯片。 通孔电极通过通孔电极，通过通孔电极的接地或通过通孔电极的信号传输分类为电源。 通过通孔电极和通过通孔电极的接地的电源由诸如铜的第一材料形成，并且通过通孔电极的信号传输由掺杂杂质的多晶硅等第二材料形成。 通过通孔电极的信号传输可以具有比通过通孔电极和通过通孔电极的接地的每个电源的直径更小的横截面，而不管其电阻率如何。

公开(公告)号：US20120126400A1

公开(公告)日：2012-05-24

申请号：US13221494

申请日：2011-08-30

Applicant: Jong-Joo Lee

Inventor： Jong-Joo Lee

IPC: H01L23/498 ,  H01L21/50

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/481 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544

Abstract: A semiconductor package may include a package substrate, a first semiconductor chip and a second semiconductor chip. The first semiconductor chip may be arranged on the package substrate. The first semiconductor chip may have a plug electrically connected to the package substrate and at least one insulating hole arranged around the plug. The second semiconductor chip may be arranged on the first semiconductor chip. The second semiconductor chip may be electrically connected to the plug. Thus, the insulating hole and the insulating member may ensure an electrical isolation between the plug and the first semiconductor chip, and between the plugs.

Abstract translation: 半导体封装可以包括封装衬底，第一半导体芯片和第二半导体芯片。 第一半导体芯片可以布置在封装衬底上。 第一半导体芯片可以具有电连接到封装基板的插头和布置在插头周围的至少一个绝缘孔。 第二半导体芯片可以布置在第一半导体芯片上。 第二半导体芯片可以电连接到插头。 因此，绝缘孔和绝缘构件可以确保插头和第一半导体芯片之间以及插头之间的电隔离。

公开(公告)号：US08178969B2

公开(公告)日：2012-05-15

申请号：US12401699

申请日：2009-03-11

Applicant: Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

Inventor： Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

IPC: H01L23/485

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05085 ,  H01L2224/05558 ,  H01L2224/0603 ,  H01L2224/06136 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.

Abstract translation: 倒装芯片封装可以包括衬底，半导体芯片，主凸块结构和辅助凸块结构。 基板具有电路图案。 半导体芯片布置在衬底上。 半导体芯片包括具有半导体结构的主体，与半导体结构电连接以主要控制半导体结构的主焊盘以及与半导体结构电连接以提供半导体结构的辅助控制的辅助焊盘。 主凸块结构插入在半导体芯片和基板之间以将电路图案与主焊盘电连接。 辅助凸块结构可以插入在半导体芯片和衬底之间以将电路图案与辅助焊盘电连接。

公开(公告)号：US20120104627A1

公开(公告)日：2012-05-03

申请号：US13344634

申请日：2012-01-06

Applicant: Jong-Joo Lee

Inventor： Jong-Joo Lee

IPC: H01L23/48

CPC classification number: H01L23/5286 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/1203 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2224/05552

Abstract: Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.

Abstract translation: 提供了具有直接连接到内部电路的电源/接地线的重分布金属互连的半导体芯片的实施例。 半导体芯片的实施例包括形成在半导体衬底上的内部电路。 芯片焊盘设置在半导体衬底上。 芯片焊盘通过内部互连电连接到内部电路。 钝化层设置在芯片焊盘的上方。 在钝化层上设置重新分布的金属互连。 再分布的金属互连通过穿孔至少钝化层的通孔和芯片焊盘开口将内部互连直接连接到芯片焊盘。 还提供了制造半导体芯片的方法。

公开(公告)号：US20120049351A1

公开(公告)日：2012-03-01

申请号：US13198738

申请日：2011-08-05

Applicant: JONG-JOO LEE

Inventor： JONG-JOO LEE

IPC: H01L23/498 ,  H01L23/48

CPC classification number: H05K1/111 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06152 ,  H01L2224/06154 ,  H01L2224/06179 ,  H01L2224/06517 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/1712 ,  H01L2224/17517 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/181 ,  H05K1/0271 ,  H05K3/3436 ,  H05K2201/09418 ,  H05K2201/09781 ,  H05K2201/10674 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A package substrate includes an insulating substrate, a functional pattern and a main dummy pattern. A semiconductor chip is arranged on the insulating substrate. The functional pattern is formed on the insulating substrate. The functional pattern is electrically connected to the semiconductor chip. The main dummy pattern is formed on a portion of the insulating substrate at least of to the outside of and/or adjacent the functional pattern in a path of stress generated by a difference between thermal expansion coefficient of the insulating substrate and the semiconductor chip, so as to divert the stress away from the functional pattern. Thus, the stress is not concentrated on the functional pattern. As a result, damage to the functional bump caused by the stress is prevented.

Abstract translation: 封装基板包括绝缘基板，功能图案和主虚拟图案。 半导体芯片布置在绝缘基板上。 功能图案形成在绝缘基板上。 功能图案电连接到半导体芯片。 主绝缘基板的绝缘基板的至少一部分在由绝缘基板和半导体芯片的热膨胀系数之差产生的应力路径中至少在功能图案的外侧和/或相邻的部分上形成，因此， 将压力从功能模式转移出去。 因此，应力不集中在功能图案上。 结果，防止了由应力引起的功能性凸起的损坏。

公开(公告)号：US08044302B2

公开(公告)日：2011-10-25

申请号：US11945874

申请日：2007-11-27

Applicant: Jong-Joo Lee

Inventor： Jong-Joo Lee

IPC: H05K1/03

CPC classification number: H05K1/0228 ,  H01L23/13 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/4824 ,  H01L2924/30107 ,  H05K1/0248 ,  H05K2201/09336 ,  H05K2201/09727 ,  H05K2201/10734 ,  H01L2924/00

Abstract: Provided is a printed circuit board having coplanar LC balance, comprising: an insulation layer, printed circuit patterns formed on the insulation layer, power source wirings supplying power in the printed circuit patterns, and at least three signal wirings formed between the power source wirings, wherein widths of signal wirings far from the power source wirings are wider than widths of signal wirings adjacent to the power source wirings to achieve LC balance, thereby reducing the skew between signal wirings and improving the quality of signal transfer.

Abstract translation: 提供一种具有共面LC平衡的印刷电路板，包括：绝缘层，形成在绝缘层上的印刷电路图案，在印刷电路图案中供电的电源布线以及形成在电源布线之间的至少三个信号布线， 其中远离电源布线的信号布线的宽度宽于与电源布线相邻的信号布线的宽度，以实现LC平衡，从而减少信号布线之间的偏斜并提高信号传输的质量。

公开(公告)号：US07821127B2

公开(公告)日：2010-10-26

申请号：US11033845

申请日：2005-01-13

Applicant: Jong-Joo Lee ,  Young-Hee Song

Inventor： Jong-Joo Lee ,  Young-Hee Song

IPC: H01L23/34

CPC classification number: H05K1/181 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/19105 ,  H05K2201/10159 ,  H05K2201/10734 ,  H05K2203/1572 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method and apparatus of fabricating a semiconductor device are disclosed. The semiconductor device may include a buffer chip package having a buffer chip mounted on a buffer chip substrate and at least one memory package mounted on the buffer chip substrate, wherein the at least one memory package may include a plurality of memory chips. Further, the buffer chip package may have a plurality of external connection terminals.

Abstract translation: 公开了制造半导体器件的方法和装置。 半导体器件可以包括缓冲芯片封装，其具有安装在缓冲芯片基板上的缓冲芯片和安装在缓冲芯片基板上的至少一个存储器封装，其中所述至少一个存储器封装可以包括多个存储器芯片。 此外，缓冲芯片封装可以具有多个外部连接端子。

公开(公告)号：US07768115B2

公开(公告)日：2010-08-03

申请号：US12267343

申请日：2008-11-07

Applicant: Jong-Joo Lee ,  Dong-Ho Lee

Inventor： Jong-Joo Lee ,  Dong-Ho Lee

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/66 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided are a stack chip and a stack chip package having the stack chip. Internal circuits of two semiconductor chips are electrically connected to each other through an input/output buffer connected to an external connection terminal. The semiconductor chip has chip pads, input/output buffers and internal circuits connected through circuit wirings. The semiconductor chip also has connection pads connected to the circuit wirings connecting the input/output buffers to the internal circuits. The semiconductor chips include a first chip and a second chip. The connection pads of the first chip are electrically connected to the connection pads of the second chip through electrical connection means. Input signals input through the external connection terminals are input to the internal circuits of the first chip or the second chip via the chip pads and the input/output buffers of the first chip, and the connection pads of the first chip and the second chip.

Abstract translation: 提供了具有堆叠芯片的堆叠芯片和堆叠芯片封装。 两个半导体芯片的内部电路通过连接到外部连接端子的输入/输出缓冲器彼此电连接。 半导体芯片具有芯片焊盘，输入/输出缓冲器和通过电路布线连接的内部电路。 半导体芯片还具有连接到将输入/输出缓冲器连接到内部电路的电路布线的连接焊盘。 半导体芯片包括第一芯片和第二芯片。 第一芯片的连接焊盘通过电连接装置电连接到第二芯片的连接焊盘。 通过外部连接端子输入的输入信号经由芯片焊盘和第一芯片的输入/输出缓冲器以及第一芯片和第二芯片的连接焊盘输入到第一芯片或第二芯片的内部电路。

公开(公告)号：US20090230549A1

公开(公告)日：2009-09-17

申请号：US12401699

申请日：2009-03-11

Applicant: Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

Inventor： Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

IPC: H01L23/485

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05085 ,  H01L2224/05558 ,  H01L2224/0603 ,  H01L2224/06136 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.

Abstract translation: 倒装芯片封装可以包括衬底，半导体芯片，主凸块结构和辅助凸块结构。 基板具有电路图案。 半导体芯片布置在衬底上。 半导体芯片包括具有半导体结构的主体，与半导体结构电连接以主要控制半导体结构的主焊盘以及与半导体结构电连接以提供半导体结构的辅助控制的辅助焊盘。 主凸块结构插入在半导体芯片和基板之间以将电路图案与主焊盘电连接。 辅助凸块结构可以插入在半导体芯片和衬底之间以将电路图案与辅助焊盘电连接。