利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

103 条记录 (耗时 0.016 秒)

    Amplifier circuit having constant output swing range and stable delay time
    73.
    发明授权
    Amplifier circuit having constant output swing range and stable delay time 失效
    放大器电路具有恒定的输出摆幅范围和稳定的延迟时间

    公开(公告)号：US07187214B2

    公开(公告)日：2007-03-06

    申请号：US11071433

    申请日：2005-03-03

    申请人： Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

    发明人： Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

    IPC分类号： H03K5/22

    CPC分类号： H03K3/356139

    摘要： Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal reference signal with a predetermined voltage level and maintains constant the amount of a first current, and the second bias unit receives an external reference signal, responds to a control voltage, and controls the amount of a second current to be the same as the amount of the first current, and the comparison unit compares a voltage level of a first node with a voltage level of a second node, and controls a voltage level of the control voltage according to the comparison result, and the amplifier unit compares a voltage level of an external input signal with a voltage level of the external reference signal, amplifies and outputs a voltage difference between the two compared signals, responds to the control voltage, and controls the amount of a third current to be the same as the amount of the first current although the level of the external reference signal is varied, such that the amplifier circuit and a circuit for receiving data can maintain a constant output swing range and a stable delay time irrespective of variations in the voltage levels of the external input signal or the external reference signal.

    摘要翻译： 提供了具有恒定的输出摆幅范围和稳定延迟时间的放大器电路，其中放大器电路包括第一偏置单元，第二偏置单元，比较单元和放大器单元，并且第一偏置单元响应内部 具有预定电压电平的参考信号并且保持第一电流的量的恒定，并且第二偏置单元接收外部参考信号，响应于控制电压，并且将第二电流的量控制为与第 第一电流和比较单元将第一节点的电压电平与第二节点的电压电平进行比较，并且根据比较结果控制控制电压的电压电平，并且放大器单元将电压电平 具有外部参考信号电压电平的外部输入信号，放大并输出两个比较信号之间的电压差，响应控制电压，并控制 尽管外部参考信号的电平变化，但是第三电流的量与第一电流的量相同，使得放大器电路和用于接收数据的电路可以保持恒定的输出摆幅范围和稳定的 延迟时间，而不管外部输入信号或外部参考信号的电压电平的变化。

    Synchronous mirror delay circuit and semiconductor integrated circuit device having the same
    76.
    发明授权
    Synchronous mirror delay circuit and semiconductor integrated circuit device having the same 失效
    同步镜延迟电路和具有该同步镜延迟电路的半导体集成电路器件

    公开(公告)号：US06992514B2

    公开(公告)日：2006-01-31

    申请号：US10790601

    申请日：2004-03-01

    申请人： Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

    发明人： Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

    IPC分类号： H03L7/00

    CPC分类号： H03K5/135

    摘要： Disclosed is a synchronous mirror delay circuit for generating an internal clock signal synchronized with an external clock signal, comprising: a clock buffer circuit that generates a reference clock signal in response to the external clock signal; a delay monitor circuit that delays the reference clock signal; a forward delay array for delaying an output clock signal of the delay monitor circuit to generate delay clock signals; a mirror control circuit that receives the delay clock signals and the reference clock signal to detect one delay clock signal synchronized with the reference clock signal among the delay clock signals; a backward delay array that delays the delay clock signal detected by the mirror control circuit to output a synchronous clock signal; a delay circuit that delays an asynchronous clock signal output through the forward delay array; and a clock driving circuit that outputs the delayed asynchronous clock signal as the internal clock signal when the reference clock signal is not synchronized with one of the delay clock signals.

    摘要翻译： 公开了一种用于产生与外部时钟信号同步的内部时钟信号的同步镜延迟电路，包括：时钟缓冲电路，其响应于外部时钟信号产生参考时钟信号; 延迟监视电路，延迟参考时钟信号; 用于延迟延迟监视电路的输出时钟信号以产生延迟时钟信号的正向延迟阵列; 接收所述延迟时钟信号和所述参考时钟信号以在所述延迟时钟信号中检测与所述参考时钟信号同步的一个延迟时钟信号的镜像控制电路; 后延迟阵列，其延迟由所述镜控制电路检测到的延迟时钟信号，以输出同步时钟信号; 延迟电路，延迟通过前向延迟阵列输出的异步时钟信号; 以及时钟驱动电路，当所述参考时钟信号与所述延迟时钟信号之一不同步时，输出所述延迟异步时钟信号作为所述内部时钟信号。

    Programmable impedance controller and method for operating
    77.
    发明申请
    Programmable impedance controller and method for operating 有权
    可编程阻抗控制器和操作方法

    公开(公告)号：US20060006903A1

    公开(公告)日：2006-01-12

    申请号：US11175634

    申请日：2005-07-05

    申请人： Myung-Hun Choi ,  Nam-Seog Kim ,  Chul-Sung Park

    发明人： Myung-Hun Choi ,  Nam-Seog Kim ,  Chul-Sung Park

    IPC分类号： H03K19/003

    CPC分类号： H04L25/0278 ,  H03K19/0005

    摘要： A programmable impedance controller and a method of operating prevent or substantially reduce internal noise and an influence from external noise lasting for a long time. The programmable impedance controller for comparing a pad voltage of a pad connected to an external determination impedance with a reference voltage, and for outputting an impedance control signal, and for performing a digital coding to an impedance code corresponding to the impedance control signal, includes a clock controller and a counter. The clock controller outputs a first clock signal in a reset mode and outputs a second clock signal in an operating mode, in response to an applied clock signal. The counter sequentially updates code data, one code step per clock period, in response to the first clock signal in the reset mode, and outputs update code data. In an operating mode, the counter outputs the update code data updated in the reset mode in response to the second clock signal.

    摘要翻译： 可编程阻抗控制器和操作方法可以防止或显着降低内部噪声以及长时间持续的外部噪声的影响。 可编程阻抗控制器，用于将连接到外部确定阻抗的焊盘的焊盘电压与参考电压进行比较，并用于输出阻抗控制信号，以及对与阻抗控制信号相对应的阻抗代码执行数字编码，包括： 时钟控制器和计数器。 时钟控制器以复位模式输出第一时钟信号，并且响应于所施加的时钟信号而在操作模式下输出第二时钟信号。 响应于复位模式中的第一时钟信号，计数器依次更新代码数据，每时钟周期的一个代码步长，并输出更新代码数据。 在操作模式中，计数器响应于第二时钟信号输出以复位模式更新的更新代码数据。

    Digitally controllable internal clock generating circuit of semiconductor memory device and method for same
    78.
    发明授权
    Digitally controllable internal clock generating circuit of semiconductor memory device and method for same 有权

    公开(公告)号：US06661272B2

    公开(公告)日：2003-12-09

    申请号：US10041060

    申请日：2002-01-07

    申请人： Nam-Seog Kim ,  Yong-Jin Yoon

    发明人： Nam-Seog Kim ,  Yong-Jin Yoon

    IPC分类号： H03K300

    CPC分类号： G11C7/222 ,  G11C7/22

    摘要： An internal clock generating circuit of a semiconductor device includes: a delay chain having a plurality of delay units for generating multi-phase clocks by adjusting an input clock; a thermometer for outputting a thermometer code value in response to an input selection data; a multiplexer for selectively outputting one of a plurality of clocks input from the delay chain in response to the thermometer code value of the thermometer; and a pulse regenerator for outputting an adjusted internal clock by restoring a pulse form of the clock output from the multiplexer into its original state and controlling the delay thereof as much as desired.

    Programmable impedance control circuit
    79.
    发明授权
    Programmable impedance control circuit 有权
    可编程阻抗控制电路

    公开(公告)号：US06661250B2

    公开(公告)日：2003-12-09

    申请号：US10357841

    申请日：2003-02-04

    申请人： Nam-Seog Kim ,  Uk-Rae Cho

    发明人： Nam-Seog Kim ,  Uk-Rae Cho

    IPC分类号： H03K1716

    CPC分类号： H03H21/0001 ,  H03H11/405

    摘要： Disclosed is a programmable impedance control circuit, comprising a voltage divider, the voltage divider comprising an MOS array supplied with a first voltage and an external resistance having an external impedance equal to N times said external resistance. The voltage divider outputs a second voltage. A reference voltage generator is provided for generating a third voltage corresponding to N/(N+M) times said first voltage as a reference voltage for said second voltage, and wherein M times internal impedance is used for N times external impedance (N=M or N≠M).

    摘要翻译： 公开了一种可编程阻抗控制电路，包括分压器，该分压器包括提供有第一电压的MOS阵列和具有等于所述外部电阻的N倍的外部阻抗的外部电阻。 分压器输出第二个电压。 参考电压发生器用于产生对应于所述第一电压的N /（N + M）倍的第三电压作为所述第二电压的参考电压，并且其中M次内部阻抗用于N次外部阻抗（N = M 或N≤M）。

    Method for generating internal clock of semiconductor memory device and circuit thereof
    80.
    发明授权
    Method for generating internal clock of semiconductor memory device and circuit thereof 失效

    公开(公告)号：US06577175B2

    公开(公告)日：2003-06-10

    申请号：US10041091

    申请日：2002-01-07

    申请人： Nam-Seog Kim ,  Jung-Woo Park

    发明人： Nam-Seog Kim ,  Jung-Woo Park

    IPC分类号： H03L706

    CPC分类号： G11C7/222 ,  G11C7/22 ,  H03L7/0812

    摘要： The invention relates to a semiconductor memory device and a method for generating an internal clock, the circuit of the semiconductor device including: a receiver for receiving an external clock; a delay compensation circuit for receiving an output of the receiver and delaying it by as much as the compensation delay time and control delay time subtracted out of a cycle of the external clock; an external control delay part for delaying an output of the delay compensation circuit by as much as the control delay time and unit increase/decrease delay time in response to an external control code; and an internal clock driver for driving an output of the external control delay part and generating an internal clock centered to externally applied data, thereby performing an accurate timing control to an external clock without loss of performance.