公开(公告)号：US10026682B2

公开(公告)日：2018-07-17

申请号：US15369659

申请日：2016-12-05

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

IPC: H01L23/498 ,  H01L21/48

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

公开(公告)号：US20180019558A1

公开(公告)日：2018-01-18

申请号：US15716356

申请日：2017-09-26

Applicant: INTEL CORPORATION

Inventor： Dhanya Athreya ,  Gaurav Chawla ,  Kemal Aygun ,  Glen P. Gordon ,  Sarah M. Canny ,  Jeffory L. Smalley ,  Srikant Nekkanty ,  Michael Garcia ,  Joshua D. Heppner

IPC: H01R33/76 ,  H01L23/32 ,  H01L23/498

CPC classification number: H01R33/7685 ,  H01L23/32 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards socket contact techniques and configurations. In one embodiment, an apparatus may include a socket substrate having a first side and a second side disposed opposite to the first side, an opening formed through the socket substrate, an electrical contact disposed in the opening and configured to route electrical signals between the first side and the second side of the socket substrate, the electrical contact having a cantilever portion that extends beyond the first side, wherein the first side and surfaces of the socket substrate in the opening are plated with a metal. Other embodiments may be described and/or claimed.

公开(公告)号：US20170221727A9

公开(公告)日：2017-08-03

申请号：US14974726

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Tao Wu ,  Zhiguo Qian ,  Kemal Aygun

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1517 ,  H01L2924/15311

Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described.

公开(公告)号：US20160254629A1

公开(公告)日：2016-09-01

申请号：US14764931

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Dhanya Athreya ,  Gaurav Chawla ,  Kemal Aygun ,  Glen P. Gordon ,  Sarah M. Canny ,  Jeffory L. Smalley ,  Srikant Nekkanty ,  Michael Garcia ,  Joshua D. Heppner

IPC: H01R33/76 ,  H01L23/32

CPC classification number: H01R33/7685 ,  H01L23/32 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards socket contact techniques and configurations. In one embodiment, an apparatus may include a socket substrate having a first side and a second side disposed opposite to the first side, an opening formed through the socket substrate, an electrical contact disposed in the opening and configured to route electrical signals between the first side and the second side of the socket substrate, the electrical contact having a cantilever portion that extends beyond the first side, wherein the first side and surfaces of the socket substrate in the opening are plated with a metal. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例针对套接触接触技术和配置。 在一个实施例中，装置可以包括具有第一侧和与第一侧相对设置的第二侧的插座衬底，通过插座衬底形成的开口，设置在开口中并被配置为在第一 所述电接触件具有延伸超过所述第一侧面的悬臂部分，其中所述开口中的所述插座基板的所述第一侧面和所述表面镀有金属。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160181189A1

公开(公告)日：2016-06-23

申请号：US14943880

申请日：2015-11-17

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于集成电路（IC）组件中用于串扰缓解的地面通过群集的技术和配置。 在一些实施例中，IC封装组件可以包括被配置为在管芯和第二封装衬底之间路由输入/输出（I / O）信号和接地的第一封装衬底。 第一封装衬底可以包括设置在第一封装衬底的一侧上的多个触点和相同的通孔层的至少两个接地通孔，并且所述至少两个接地通孔可以形成一组接地通孔， 个人联系。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09232686B2

公开(公告)日：2016-01-05

申请号：US14227929

申请日：2014-03-27

Applicant: INTEL CORPORATION

Inventor： Digvijay A. Raorane ,  Kemal Aygun ,  Daniel N. Sobieski ,  Drew W. Delaney

IPC: H05K7/00 ,  H05K9/00 ,  H05K1/02 ,  C23C14/34 ,  H05K3/00 ,  C23C14/14

CPC classification number: H05K3/007 ,  C23C14/14 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/1815 ,  H01L2924/18162 ,  H05K1/0219 ,  H05K1/185 ,  H05K3/02 ,  H05K3/30 ,  H05K3/4682 ,  H05K2201/0715 ,  H05K2203/1469 ,  H05K2203/308 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/83005

Abstract: An apparatus including a die including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the die, the build-up carrier including a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and an interference shield including a conductive material disposed on the die and a portion of the build-up carrier. The apparatus may be connected to a printed circuit board. A method including forming a build-up carrier adjacent a device side of a die including a plurality of alternating layers of patterned conductive material and insulating material; and forming a interference shield on a portion of the build-up carrier.

Abstract translation: 一种包括模具的装置，包括具有限定模具的厚度的接触点和侧壁的装置侧; 耦合到管芯的积聚载体，所述堆积载体包括多个图案化导电材料和绝缘材料的交替层，其中图案化导电材料层中的至少一层耦合到 死; 以及包括设置在管芯上的导电材料和积聚载体的一部分的干涉屏蔽。 该装置可以连接到印刷电路板。 一种方法，包括在包括图案化导电材料和绝缘材料的多个交替层的模具的器件侧附近形成堆积载体; 以及在积聚载体的一部分上形成干涉屏蔽。

公开(公告)号：US09232639B2

公开(公告)日：2016-01-05

申请号：US13707113

申请日：2012-12-06

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Tao Wu ,  Zhiguo Qian ,  Kemal Aygun

IPC: H05K7/10 ,  H05K1/02 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K1/0298 ,  H01L21/4846 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/0216 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T29/49155 ,  H01L2924/00

Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described.

Abstract translation: 本文描述的一些实施例包括形成这种装置的装置和方法。 一个这样的实施例可以包括具有要耦合到半导体管芯的焊盘的布线布置，其中第一迹线耦合到焊盘之间的第一焊盘，以及耦合到焊盘之间的第二焊盘的第二迹线。 第一和第二迹线可以具有不同的厚度。 描述包括附加装置和方法的其他实施例。

公开(公告)号：US12062616B2

公开(公告)日：2024-08-13

申请号：US18377183

申请日：2023-10-05

Applicant: Intel Corporation

Inventor： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/075 ,  H01L25/16

CPC classification number: H01L23/5381 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/0753 ,  H01L25/167 ,  H01L2224/81 ,  H01L2924/181

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US20240222328A1

公开(公告)日：2024-07-04

申请号：US18148543

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Nisha Ananthakrishnan ,  Kemal Aygun ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B12/00

CPC classification number: H01L25/0657 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H10B12/39

Abstract: Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit, a second IC die; a third IC die; and a package substrate. The first IC die comprises: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The second portion is surrounded by the first portion in plan view, the first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.

公开(公告)号：US11901280B2

公开(公告)日：2024-02-13

申请号：US17956766

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L23/49816 ,  H01L23/49838 ,  H01L21/486 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.