公开(公告)号：US20130285156A1

公开(公告)日：2013-10-31

申请号：US13926417

申请日：2013-06-25

Applicant: International Business Machines Corporation

Inventor： Ming Cai ,  Dechao Guo ,  Chung-Hsun Lin ,  Chun-Chen Yeh

IPC: H01L27/088

CPC classification number: H01L27/0886 ,  H01L21/3086 ,  H01L21/845 ,  H01L27/1211

Abstract: A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.

Abstract translation: 一种形成集成电路（IC）的方法包括在基板上形成第一和第二多个间隔物，其中所述基板包括硅层，并且其中所述第一多个间隔件的厚度不同于所述第二 多个间隔物; 并且使用所述第一和第二多个间隔物作为掩模来蚀刻所述衬底中的所述硅层，其中所述蚀刻的硅层形成第一多个和第二多个鳍状场效应晶体管（FINFET）沟道区，并且其中所述第一多个 FINFET通道区域各自具有对应于第一多个间隔物的厚度的相应厚度，并且其中第二多个FINFET沟道区域各自具有对应于第二多个间隔物的厚度的相应厚度。

公开(公告)号：US20130149823A1

公开(公告)日：2013-06-13

申请号：US13765830

申请日：2013-02-13

Applicant: International Business Machines Corporation

Inventor： Stephen W. Bedell ,  Josephine B. Chang ,  Chung-Hsun Lin

IPC: H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/66477 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7849

Abstract: A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner.

Abstract translation: 公开了一种制造集成电路的方法和在应力衬垫上具有硅的集成电路。 在一个实施例中，该方法包括提供包括嵌入式一次性层的半导体衬底，以及去除该一次性层的至少一部分以在衬底内形成空隙。 该方法还包括在该空隙中沉积材料以形成应力衬垫，以及在衬底的外部半导体层上形成晶体管。 该半导体层将晶体管与应力衬垫分开。 在一个实施例中，衬底包括隔离区; 并且所述去除包括在所述隔离区域中形成凹部，以及经由所述凹部去除所述一次性层的至少一部分。 在一个实施例中，沉积包括通过凹部将材料沉积在空隙中。 端盖可以形成在应力衬垫的端部处的凹部中。

公开(公告)号：US10381452B2

公开(公告)日：2019-08-13

申请号：US15797315

申请日：2017-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Chung-Hsun Lin ,  Shreesh Narasimha ,  Claude Ortolland ,  Jonathan T. Shaw

IPC: H01L29/423 ,  H01L29/51 ,  H01L21/265 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L21/426 ,  H01L21/8234 ,  H01L21/3115 ,  H01L21/324 ,  H01L29/40 ,  H01L21/84 ,  H01L29/78 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/417

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

公开(公告)号：US10256139B2

公开(公告)日：2019-04-09

申请号：US15467665

申请日：2017-03-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Markus Brink ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  HsinYu Tsai

IPC: H01L21/31 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  G03F7/00

Abstract: A method of forming metal lines that are aligned to underlying metal features that includes forming a neutral layer atop a hardmask layer that is overlying a dielectric layer. The neutral layer is composed of a neutral charged di-block polymer. Patterning the neutral layer, the hardmask layer and the dielectric layer to provide openings that are filled with a metal material to provide metal features. A self-assembled di-block copolymer material is deposited on a patterned surface of the neutral layer and the metal features. The self-assembled di-block copolymer material includes a first block composition with a first affinity for alignment to the metal features. The first block composition of the self-assembled di-block copolymer is converted to a metal that is self-aligned to the metal features.

公开(公告)号：US20170229353A1

公开(公告)日：2017-08-10

申请号：US15494992

申请日：2017-04-24

Applicant: International Business Machines Corporation

Inventor： Chung-Hsun Lin ,  Yu-Shiang Lin ,  Shih-Hsien Lo ,  Joel A. Silberman

IPC: H01L21/84 ,  H01L29/786 ,  H01L21/768 ,  H01L23/48 ,  H01L27/12 ,  H01L21/3065

CPC classification number: H01L29/78696 ,  H01L21/3065 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78651 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.

公开(公告)号：US20170084745A1

公开(公告)日：2017-03-23

申请号：US15365538

申请日：2016-11-30

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78696

Abstract: At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor nanowire such that the at least one semiconductor nanowire is suspended. A temporary fill material is deposited over the at least one semiconductor nanowire, and is planarized to physically expose top surfaces of the pair of semiconductor pad portions. Trenches are formed within the pair of semiconductor pad portions, and are filled with stress-generating materials. The temporary fill material is subsequently removed. The at least one semiconductor nanowire is strained along the lengthwise direction with a tensile strain or a compressive strain.

公开(公告)号：US09559010B2

公开(公告)日：2017-01-31

申请号：US15075944

申请日：2016-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Chung-Hsun Lin ,  Shreesh Narasimha ,  Claude Ortolland ,  Jonathan T. Shaw

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/40 ,  H01L29/51 ,  H01L21/265 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L21/426 ,  H01L21/3115 ,  H01L21/324

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02323 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/426 ,  H01L21/823462 ,  H01L21/845 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract translation: 公开了一种用于在高k MOSFET中减小栅极感应漏极泄漏的非对称高k电介质和制造方法。 该方法包括在栅极结构的高k电介质侧壁上执行注入工艺。 该方法还包括进行氧退火处理，以在栅极结构的漏极侧生长氧化物区域，同时抑制邻近源极区域的栅极结构的源极上的氧化物生长。

公开(公告)号：US09412667B2

公开(公告)日：2016-08-09

申请号：US14553521

申请日：2014-11-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Chung-Hsun Lin ,  Shreesh Narasimha ,  Claude Ortolland ,  Jonathan T. Shaw

IPC: H01L21/8234 ,  H01L29/51 ,  H01L21/265 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L21/02 ,  H01L21/426

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02323 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/426 ,  H01L21/823462 ,  H01L21/845 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract translation: 公开了一种用于在高k MOSFET中减小栅极感应漏极泄漏的非对称高k电介质和制造方法。 该方法包括在栅极结构的高k电介质侧壁上执行注入工艺。 该方法还包括进行氧退火处理，以在栅极结构的漏极侧生长氧化物区域，同时抑制邻近源极区域的栅极结构的源极上的氧化物生长。

公开(公告)号：US20160181394A1

公开(公告)日：2016-06-23

申请号：US14578768

申请日：2014-12-22

Applicant: International Business Machines Corporation

Inventor： Pranita Kerber ,  Chung-Hsun Lin ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66522 ,  H01L29/1083 ,  H01L29/205 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834

Abstract: Techniques for controlling short channel effects in III-V MOSFETs through the use of a halo-doped bottom (III-V) barrier layer are provided. In one aspect, a method of forming a MOSFET device is provided. The method includes the steps of: forming a III-V barrier layer on a substrate; forming a III-V channel layer on a side of the III-V barrier layer opposite the substrate, wherein the III-V barrier layer is configured to confine charge carriers in the MOSFET device to the III-V channel layer; forming a gate stack on a side of the III-V channel layer opposite the III-V barrier layer; and forming halo implants in the III-V barrier layer on opposite sides of the gate stack. A MOSFET device is also provided.

Abstract translation: 提供了通过使用卤素掺杂的底部（III-V）阻挡层来控制III-V MOSFET中的短沟道效应的技术。 在一个方面，提供了一种形成MOSFET器件的方法。 该方法包括以下步骤：在衬底上形成III-V阻挡层; 在与衬底相对的III-V阻挡层的一侧上形成III-V沟道层，其中III-V势垒层被配置为将MOSFET器件中的电荷载流子限制到III-V沟道层; 在与III-V阻挡层相对的III-V沟道层的一侧上形成栅叠层; 以及在栅堆叠的相对侧上的III-V阻挡层中形成晕轮植入物。 还提供MOSFET器件。

公开(公告)号：US09250204B2

公开(公告)日：2016-02-02

申请号：US14604959

申请日：2015-01-26

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

IPC: H01L29/786 ,  H01L21/336 ,  G01N27/414 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/16 ,  H01L51/00

CPC classification number: G01N27/4145 ,  G01N27/4146 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0048

Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.