公开(公告)号：US09953846B2

公开(公告)日：2018-04-24

申请号：US15261354

申请日：2016-09-09

Applicant: Infineon Technologies AG

Inventor： Daniel Porwol ,  Edward Fuergut

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/28 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/566 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3121 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor chip is disclosed. In an embodiment, the method includes providing a carrier, providing a plurality of semiconductor chips, the semiconductor chips each including a first main face and a second main face opposite to the first main face and side faces connecting the first and second main faces, placing the semiconductor chips on the carrier with the second main faces facing the carrier, and applying an encapsulation material to the side faces of the semiconductor chips.

公开(公告)号：US09666499B2

公开(公告)日：2017-05-30

申请号：US13664418

申请日：2012-10-31

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Edward Fuergut ,  Khalil Hosseini ,  Georg Meyer-Berg

IPC: H01L23/29 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/291 ,  H01L21/561 ,  H01L21/568 ,  H01L23/296 ,  H01L23/562 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Described are techniques related to semiconductor devices that make use of encapsulant. In one implementation, a semiconductor device may be manufactured to include at least an encapsulant that includes at least glass particles.

公开(公告)号：US20170098580A1

公开(公告)日：2017-04-06

申请号：US15378669

申请日：2016-12-14

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Gottfried Beer ,  Edward Fuergut ,  Juergen Hoegerl ,  Peter Kanschat

IPC: H01L21/78 ,  H01L21/56 ,  H01L21/48 ,  H01L21/66

CPC classification number: H01L21/78 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L22/10 ,  H01L22/14 ,  H01L23/051 ,  H01L23/31 ,  H01L23/522 ,  H01L24/96 ,  H01L25/072 ,  H01L25/115 ,  H01L27/02 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: Method for producing chip assemblies that include semiconductor chip arrangements, each semiconductor chip arrangement including a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.

公开(公告)号：US09196568B2

公开(公告)日：2015-11-24

申请号：US14042750

申请日：2013-10-01

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Carsten Ahrens ,  Damian Sojka ,  Andre Schmenn ,  Edward Fuergut

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a die including at least one electronic component and a first terminal on a first side of the die and a second terminal on a second side of the die opposite the first side, wherein the first side being the main processing side of the die, and the die further including at least a third terminal on the second side; a first electrically conductive structure providing current flow from the third terminal on second side of the die to the first side through the die; a second electrically conductive structure on the first side of the die laterally coupling the second terminal with the first electrically conductive structure; and an encapsulation material disposed at least over the first side of the die covering the first terminal and the second electrically conductive structure.

Abstract translation: 提供了一种安排。 该装置可以包括：模具，其包括至少一个电子部件和在模具的第一侧上的第一端子，以及在模具的与第一侧相对的第二侧上的第二端子，其中第一侧是主要处理侧 所述管芯和所述管芯还包括在所述第二侧上的至少第三端子; 第一导电结构，其提供从模具的第二侧上的第三端子到通过模具的第一侧的电流; 在所述模具的第一侧上的第二导电结构将所述第二端子与所述第一导电结构横向地联接; 以及封装材料，其至少设置在覆盖所述第一端子和所述第二导电结构的所述管芯的所述第一侧的上方。

公开(公告)号：US09184066B2

公开(公告)日：2015-11-10

申请号：US13678577

申请日：2012-11-16

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess ,  Bernd Roemer ,  Edward Fuergut

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L21/565 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/495 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/552 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099

Abstract: A chip arrangement is provided, the chip arrangement including: a carrier; a chip disposed over the carrier, the chip including one or more contact pads, wherein a first contact pad of the one or more contact pads is electrically contacted to the carrier; a first encapsulation material at least partially surrounding the chip; and a second encapsulation material at least partially surrounding the first encapsulation material.

Abstract translation: 提供了芯片布置，芯片布置包括：载体; 芯片，其设置在所述载体上方，所述芯片包括一个或多个接触焊盘，其中所述一个或多个接触焊盘的第一接触焊盘与所述载体电接触; 至少部分地围绕所述芯片的第一封装材料; 以及至少部分地围绕所述第一包封材料的第二包封材料。

公开(公告)号：US20150061048A1

公开(公告)日：2015-03-05

申请号：US14011566

申请日：2013-08-27

Applicant: Infineon Technologies AG

Inventor： Irmgard Escher-Poeppel ,  Edward Fuergut ,  Alfons Dehe

IPC: H04R1/02 ,  H04R31/00 ,  H04R19/00

CPC classification number: H04R1/021 ,  H04R1/086 ,  H04R19/005 ,  H04R31/006 ,  H04R2201/003 ,  H04R2201/02 ,  H04R2231/003

Abstract: A packaged MEMS device may include an embedding arrangement, a MEMS device disposed in the embedding arrangement, a sound port disposed in the embedding arrangement and acoustically coupled to the MEMS device, and a grille within the sound port. Some embodiments relate to a sound transducer component including an embedding material and a substrate-stripped MEMS die embedded into the embedding material. The MEMS die may comprise a diaphragm for sound transduction. The sound transducer component may further comprise a sound port within the embedding material in fluidic or acoustic contact with the diaphragm. Further embodiments relate to a method for packaging a MEMS device or to a method for manufacturing a sound transducer component.

Abstract translation: 封装的MEMS器件可以包括嵌入布置，布置在嵌入布置中的MEMS器件，布置在嵌入布置中并声耦合到MEMS器件的声音端口和声音端口内的格栅。 一些实施例涉及包括嵌入材料和嵌入到嵌入材料中的剥离衬底的MEMS芯片的声音传感器部件。 MEMS管芯可以包括用于声音传递的隔膜。 声音传感器部件还可以包括与隔膜流体或声学接触的嵌入材料内的声音端口。 另外的实施例涉及用于封装MEMS装置的方法或用于制造声换能器部件的方法。

公开(公告)号：US20150028436A1

公开(公告)日：2015-01-29

申请号：US14515304

申请日：2014-10-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Edward Fuergut ,  Horst Theuss ,  Rainer Leuschner

IPC: B81B7/00 ,  B81B3/00

CPC classification number: B81B7/0041 ,  B81B3/0021 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00253 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H04R19/005 ,  H04R31/006 ,  H04R2201/003 ,  H01L2924/00

Abstract: A system and a method for forming a packaged MEMS device are disclosed. In one embodiment a packaged MEMS device includes a MEMS device having a first main surface with a first area along a first direction and a second direction, a membrane disposed on the first main surface of the MEMS device and a backplate adjacent to the membrane. The packaged MEMS device further includes an encapsulation material that encapsulates the MEMS device and that defines a back volume, the back volume having a second area along the first direction and the second direction, wherein the first area is smaller than the second area.

Abstract translation: 公开了一种用于形成封装的MEMS器件的系统和方法。 在一个实施例中，封装的MEMS器件包括具有第一主表面的MEMS器件，第一主表面具有沿着第一方向的第一区域和第二方向，设置在MEMS器件的第一主表面上的膜和邻近膜的背板。 封装的MEMS器件还包括封装MEMS器件并且限定后部体积的封装材料，后部体积具有沿第一方向和第二方向的第二区域，其中第一区域小于第二区域。

公开(公告)号：US20140327071A1

公开(公告)日：2014-11-06

申请号：US14282946

申请日：2014-05-20

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Joachim Mahler

IPC: H01L29/78 ,  H01L29/66 ,  H01L23/31

CPC classification number: H01L29/7827 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3185 ,  H01L24/05 ,  H01L29/0657 ,  H01L29/66666 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

Abstract: The method includes providing a semiconductor chip having a first main face and a second main face opposite the first main face. The semiconductor chip includes an electrical device adjacent to the first main face. Material of the semiconductor chip is removed at the second main face except for a pre-defined portion so that a non-planar surface remains at the second main face.

Abstract translation: 该方法包括提供具有第一主面和与第一主面相对的第二主面的半导体芯片。 半导体芯片包括与第一主面相邻的电气装置。 除了预定义的部分之外，在第二主面处除去半导体芯片的材料，使得非平面表面保留在第二主面。

公开(公告)号：US20140264950A1

公开(公告)日：2014-09-18

申请号：US13798141

申请日：2013-03-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Rainer Steiner ,  Edward Fuergut ,  Khalil Hosseini ,  Georg Meyer-Berg ,  Joachim Mahler

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49562 ,  H01L24/06 ,  H01L24/24 ,  H01L24/25 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/24246 ,  H01L2224/2518 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/07802 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

Abstract: In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier.

Abstract translation: 在各种实施例中，提供了芯片布置。 芯片布置可以包括芯片载体和安装在芯片载体上的芯片。 芯片可以包括至少两个芯片触点和芯片与芯片载体之间的绝缘粘合剂，以将芯片粘附到芯片载体上。 所述至少两个芯片触点可以电耦合到芯片载体。

公开(公告)号：US20140197551A1

公开(公告)日：2014-07-17

申请号：US13741113

申请日：2013-01-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Daniel Porwol ,  Edward Fuergut

IPC: H01L21/56 ,  H01L23/28

CPC classification number: H01L21/566 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3121 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00

Abstract: The method comprises providing a carrier, providing a plurality of semiconductor chips, the semiconductor chips each comprising a first main face and a second main face opposite to the first main face and side faces connecting the first and second main faces, placing the semiconductor chips on the carrier with the second main faces facing the carrier, and applying an encapsulation material to the side faces of the semiconductor chips.

Abstract translation: 该方法包括提供载体，提供多个半导体芯片，所述半导体芯片各自包括第一主面和与第一主面相对的第二主面以及连接第一和第二主面的侧面，将半导体芯片放置在 载体，其中第二主面面向载体，并且将包封材料施加到半导体芯片的侧面。