公开(公告)号：US06982465B2

公开(公告)日：2006-01-03

申请号：US10433786

申请日：2001-12-06

申请人： Yukihiro Kumagai ,  Hiroyuki Ohta ,  Fumio Ootsuka ,  Shuji Ikeda ,  Takahiro Onai ,  Hideo Miura ,  Katsuhiko Ichinose ,  Toshifumi Takeda

发明人： Yukihiro Kumagai ,  Hiroyuki Ohta ,  Fumio Ootsuka ,  Shuji Ikeda ,  Takahiro Onai ,  Hideo Miura ,  Katsuhiko Ichinose ,  Toshifumi Takeda

IPC分类号： H01L29/76

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L27/092

摘要： The present invention provides a semiconductor device including n-channel field effect transistors and p-channel field effect transistors all of which have excellent drain current characteristics.In a semiconductor device including an n-channel field effect transistor 10 and a p-channel field effect transistor 30, a stress control film 19 covering a gate electrode 15 of the n-channel field effect transistor 10 undergoes film stress mainly composed of tensile stress. A stress control film 39 covering a gate electrode 15 of the p-channel field effect transistor 30 undergoes film stress mainly caused by compression stress compared to the film 19 of the n-channel field effect transistor 10. Accordingly, drain current is expected to be improved in both the n-channel field effect transistor and the p-channel field effect transistor. Consequently, the characteristics can be generally improved.

摘要翻译： 本发明提供一种包括n沟道场效应晶体管和p沟道场效应晶体管的半导体器件，其全部具有优良的漏极电流特性。 在包括n沟道场效应晶体管10和p沟道场效应晶体管30的半导体器件中，覆盖n沟道场效应晶体管10的栅电极15的应力控制膜19经受主要由拉伸应力 。 与n沟道场效应晶体管10的膜19相比，覆盖p沟道场效应晶体管30的栅电极15的应力控制膜39主要由压缩应力引起的膜应力。 因此，预期在n沟道场效应晶体管和p沟道场效应晶体管两者中都会改善漏极电流。 因此，通常可以提高特性。

公开(公告)号：US20050121727A1

公开(公告)日：2005-06-09

申请号：US10496766

申请日：2002-11-11

申请人： Norio Ishitsuka ,  Yukihiro Kumagai ,  Hideo Miura ,  Shuji Ikeda ,  Toshifumi Takeda ,  Hiroyuki Ohta

发明人： Norio Ishitsuka ,  Yukihiro Kumagai ,  Hideo Miura ,  Shuji Ikeda ,  Toshifumi Takeda ,  Hiroyuki Ohta

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/08 ,  H01L27/092 ,  H01L27/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/113

CPC分类号： H01L29/7846 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7842

摘要： The object of the present invention is to provide a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor, which has a high degree of reliability and excellent drain current characteristics. The gist of the invention for attaining the object resides in disposing a silicon nitride film to the side wall of a trench for an active region in which the n-type channel field effect transistor is formed and disposing the silicon nitride film only in the direction perpendicular to the channel direction to the sidewall of the trench for the active region of the p-type channel field effect transistor. According to the present invention, a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor of excellent current characteristics can be provided.

摘要翻译： 本发明的目的是提供一种包括n型沟道场效应晶体管和p型沟道场效应晶体管的半导体器件，其具有高可靠性和优异的漏极电流特性。 实现本发明的要点在于，在形成有n型沟道场效应晶体管的有源区的沟槽的侧壁上设置氮化硅膜，仅在垂直方向上设置氮化硅膜 到通道方向，到p型沟道场效应晶体管的有源区的沟槽的侧壁。 根据本发明，可以提供包括n型沟道场效应晶体管和具有优异电流特性的p型沟道场效应晶体管的半导体器件。

公开(公告)号：US20050062077A1

公开(公告)日：2005-03-24

申请号：US10961090

申请日：2004-10-12

申请人： Shuji Ikeda ,  Toshiaki Yamanaka ,  Kenichi Kikushima ,  Shinichiro Mitani ,  Kazushige Sato ,  Akira Fukami ,  Masaya Iida ,  Akihiro Shimizu

发明人： Shuji Ikeda ,  Toshiaki Yamanaka ,  Kenichi Kikushima ,  Shinichiro Mitani ,  Kazushige Sato ,  Akira Fukami ,  Masaya Iida ,  Akihiro Shimizu

IPC分类号： G11C11/412 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L31/113

CPC分类号： H01L27/11 ,  G11C11/412 ,  G11C11/4125 ,  H01L21/76895 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/1104 ,  Y10S257/904

摘要： A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

摘要翻译： 一种完整的CMOS型SRAM，其存储单元由六个MISFET组成，其中一对用于连接CMOS反相器的输入/输出端的局部布线由难熔金属硅化物层形成，该难熔金属硅化物层形成在构成个体的第一导电层上 存储单元的驱动MISFET，转移MISFET和负载MISFET的栅极电极，其中形成在局部布线上的参考电压线被布置成叠加在局部布线上以形成电容元件。 此外，通过在第一导电层上叠加局部布线，在局部布线和第一导电层之间形成电容元件。 此外，通过使用诸如硅化的电阻降低装置来形成局部布线。 此外，公开了用于降低转移MISFET的栅电极的电阻和用于形成局部布线的装置的手段。

公开(公告)号：US06815748B2

公开(公告)日：2004-11-09

申请号：US10761311

申请日：2004-01-22

申请人： Koichiro Ishibashi ,  Shuji Ikeda ,  Harumi Wakimoto ,  Kenichi Kuroda

发明人： Koichiro Ishibashi ,  Shuji Ikeda ,  Harumi Wakimoto ,  Kenichi Kuroda

IPC分类号： H01L27108

CPC分类号： H01L27/092

摘要： The metal layers embedded into the contact holes of various kinds in shape are used as the lines and are employed as the lines for controlling the substrate bias. The first-layer metal line layers are made thin so as to be also employed as the lines for controlling the substrate bias. Moreover, the second-layer metal line layers are employed as the copper line layers. Thereby, a semiconductor integrated circuit which allows a high-speed and low-power operation is provided with a small area and without increasing the number of the masks.

公开(公告)号：US06559037B2

公开(公告)日：2003-05-06

申请号：US09809046

申请日：2001-03-16

申请人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

发明人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

IPC分类号： H01L2120

CPC分类号： H01L21/02667 ,  C23C16/24 ,  C23C16/45523 ,  C23C16/45561 ,  C23C16/52 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/28035 ,  H01L21/28525 ,  H01L21/28556 ,  H01L29/045 ,  H01L29/4916 ,  H01L29/66757 ,  H01L31/182 ,  H01L2924/0002 ,  Y02E10/546 ,  Y02P70/521 ,  H01L2924/00

摘要： A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.

摘要翻译： 包含多晶硅薄膜的半导体器件可以通过沉积非杂质掺杂的硅薄膜来制造，其中硅薄膜的晶粒主要具有柱状结构和单个晶粒的晶体取向几乎是均匀的方向 或下层膜的界面上的杂质层，然后如果需要，沉积杂质掺杂的硅薄膜，然后进行多结晶热处理。

公开(公告)号：US06528848B1

公开(公告)日：2003-03-04

申请号：US09666772

申请日：2000-09-20

申请人： Yutaka Hoshino ,  Shuji Ikeda ,  Isao Yoshida ,  Shiro Kamohara ,  Megumi Kawakami ,  Tomoyuki Miyake ,  Masatoshi Morikawa

发明人： Yutaka Hoshino ,  Shuji Ikeda ,  Isao Yoshida ,  Shiro Kamohara ,  Megumi Kawakami ,  Tomoyuki Miyake ,  Masatoshi Morikawa

IPC分类号： H01L2972

CPC分类号： H01L29/66659 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/4827 ,  H01L23/53219 ,  H01L23/53295 ,  H01L27/0255 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/7835 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).

公开(公告)号：US06403446B1

公开(公告)日：2002-06-11

申请号：US09536447

申请日：2000-03-28

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Masayuki Kojima ,  Kota Funayama

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Masayuki Kojima ,  Kota Funayama

IPC分类号： H01L2176

CPC分类号： H01L21/76232 ,  Y10S148/05

摘要： Manufacturing a semiconductor device avoiding an increase of transistor leak current or reduction of the withstanding voltage characteristics is by at least one of: The pad oxide film is removed along the substrate surface from the upper edge of the groove over a distance ranging from 5 to 40 nm: The exposed surface of the semiconductor substrate undergoes removal by isotropic etching within 20 nm; and oxidizing a groove portion formed in a semiconductor substrate in an oxidation environment with a gas ratio of hydrogen (H2) to oxygen (O2) being less than or equal to 0.5, an increase of the curvature radius beyond 3nm is achieved without associating the risk of creation of any level difference on the substrate surface at or near the upper groove edge portions in a groove separation structure. This eliminates either an increase of transistor leak current or reduction of the withstanding voltage characteristics thereof otherwise occurring due to local electric field concentration near or around the terminate ends of a gate electrode film which in turn leads to an ability to improve electrical reliability of transistors used.

摘要翻译： 制造半导体器件避免晶体管泄漏电流的增加或耐压特性的降低是至少以下之一：衬垫氧化膜沿着衬底表面从沟槽的上边缘移除5至40的距离 nm：通过各向同性蚀刻在20nm内去除半导体衬底的暴露表面; 并且在氧（H2）与氧气（O2）的气体比小于或等于0.5的氧化环境中氧化形成在半导体衬底中的沟槽部分，实现曲率半径超过3nm的增加，而不会使风险 在槽分离结构中的上槽边缘部分处或附近在基板表面上产生任何水平差。 这消除了晶体管泄漏电流的增加或由于栅极电极膜的端部附近或周围的局部电场浓度而导致的耐压特性的降低，这进而导致提高使用的晶体管的电可靠性的能力 。

公开(公告)号：US06326284B1

公开(公告)日：2001-12-04

申请号：US08610488

申请日：1996-03-04

申请人： Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasuhide Hagiwara ,  Hiroyuki Ohta ,  Asao Nishimura

发明人： Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasuhide Hagiwara ,  Hiroyuki Ohta ,  Asao Nishimura

IPC分类号： H01L2176

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/321 ,  H01L21/76202 ,  H01L29/518

摘要： A semiconductor device produced by forming an oxide film on a substrate, heat treating the oxide film at a temperature of 800° C. or higher in an inert atmosphere, followed by conventional steps for formation of a transistor, is improved in electrical reliability due to relaxation of stress generated in the oxide film or in the surface of substrate.

摘要翻译： 通过在基板上形成氧化膜而制造的半导体装置，在惰性气氛中，在800℃以上的温度下进行氧化膜的热处理，接着是用于形成晶体管的常规步骤，由于 松弛在氧化膜或衬底表面产生的应力。

公开(公告)号：US06211004B1

公开(公告)日：2001-04-03

申请号：US09334266

申请日：1999-06-16

申请人： Shuji Ikeda ,  Toshiaki Yamanaka ,  Kenichi Kikushima ,  Shinichiro Mitani ,  Kazushige Sato ,  Akira Fukami ,  Masaya Iida ,  Akihiro Shimizu

发明人： Shuji Ikeda ,  Toshiaki Yamanaka ,  Kenichi Kikushima ,  Shinichiro Mitani ,  Kazushige Sato ,  Akira Fukami ,  Masaya Iida ,  Akihiro Shimizu

IPC分类号： H01L218234

CPC分类号： H01L27/11 ,  G11C11/412 ,  G11C11/4125 ,  H01L21/76895 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/1104 ,  Y10S257/904

摘要： A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

摘要翻译： 一种完整的CMOS型SRAM，其存储单元由六个MISFET组成，其中一对用于连接CMOS反相器的输入/输出端的局部布线由难熔金属硅化物层形成，该难熔金属硅化物层形成在构成个体的第一导电层上 存储器单元的驱动MISFET，传输MISFET和负载MISFET的栅电极，其中形成在局部布线上的参考电压线被布置成叠加在局部布线上以形成电容元件。此外， 通过在第一导电层上叠置局部布线，在局部布线和第一导电层之间形成电容元件。此外，通过使用诸如硅化的电阻降低装置形成局部布线。 此外，公开了用于降低转移MISFET的栅电极的电阻和用于形成局部布线的装置的手段。

公开(公告)号：US06204155B1

公开(公告)日：2001-03-20

申请号：US09597985

申请日：2000-06-19

申请人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

发明人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

IPC分类号： H01L2120

CPC分类号： H01L21/02667 ,  C23C16/24 ,  C23C16/45523 ,  C23C16/45561 ,  C23C16/52 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/28035 ,  H01L21/28525 ,  H01L21/28556 ,  H01L29/045 ,  H01L29/4916 ,  H01L29/66757 ,  H01L31/182 ,  H01L2924/0002 ,  Y02E10/546 ,  Y02P70/521 ,  H01L2924/00

摘要： A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.