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公开(公告)号：US07124389B2
公开(公告)日：2006-10-17
申请号：US10848102
申请日：2004-05-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： An automated wiring pattern layout method is provided. With this method, a first wiring pattern is generated with width W and extending in a first direction, and a second wiring pattern is generated with width W and extending in a direction perpendicular to the first wiring pattern in a manner such that the end thereof ends at the end portion of the first wiring pattern. Moreover, an overlapping region is generated by bending an end of either one of the first or the second wiring pattern at a right angle to produce an L-shaped extension and overlaying the first and the second wiring pattern, and a rectangular-shaped VIA pattern is generated at the overlapping region.
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72.发明授权Method of setting process parameter and method of setting process parameter and/or design rule 有权设置过程参数的方法和设置过程参数和/或设计规则的方法公开(公告)号：US07120882B2
公开(公告)日：2006-10-10
申请号：US11105431
申请日：2005-04-14
申请人： Toshiya Kotani , Satoshi Tanaka , Koji Hashimoto , Soichi Inoue , Ichiro Mori
发明人： Toshiya Kotani , Satoshi Tanaka , Koji Hashimoto , Soichi Inoue , Ichiro Mori
IPC分类号： G06F17/50
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.
摘要翻译： 公开了一种设置用于制造半导体集成电路的工艺参数的方法，包括通过使用工艺参数信息来校正第一图案以获得第二图案，第一图案是对应于半导体集成电路的设计布局的图案 ，通过使用处理参数信息来预测第三图案，在蚀刻工艺中，第三图案是对应于第二图案并且将形成在半导体晶片上的图案，通过将第三图案与第一图案进行比较来获得评估值 判定评估值是否满足预设条件，以及当评估值不满足预设条件时，改变处理参数信息。
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73.发明授权Method of manufacturing a photo mask and method of manufacturing a semiconductor device 有权制造光掩模的方法和制造半导体器件的方法公开(公告)号：US07090949B2
公开(公告)日：2006-08-15
申请号：US10724738
申请日：2003-12-02
申请人： Shigeki Nojima , Shoji Mimotogi , Satoshi Tanaka , Toshiya Kotani , Shigeru Hasebe , Koji Hashimoto , Soichi Inoue , Osamu Ikenaga
发明人： Shigeki Nojima , Shoji Mimotogi , Satoshi Tanaka , Toshiya Kotani , Shigeru Hasebe , Koji Hashimoto , Soichi Inoue , Osamu Ikenaga
IPC分类号： G01F9/00
摘要： Disclosed is a method of manufacturing a photo mask comprising preparing mask data for a mask pattern to be formed on a mask substrate, calculating edge moving sensitivity with respect to each of patterns included in the mask pattern using the mask data, the edge moving sensitivity corresponding to a difference between a proper exposure dose and an exposure dose to be set when a pattern edge varies, determining a monitor portion of the mask pattern, based on the calculated edge moving sensitivity, actually forming the mask pattern on the mask substrate, acquiring a dimension of a pattern included in that portion of the mask pattern formed on the mask substrate which corresponds to the monitor portion, determining evaluation value for the mask pattern formed on the mask substrate, based on the acquired dimension, and determining whether the evaluation value satisfies predetermined conditions.
摘要翻译： 公开了一种制造光掩模的方法，其包括：对掩模基板上形成的掩模图案准备掩模数据，使用掩模数据计算相对于包含在掩模图案中的每个图案的边缘移动灵敏度，边缘移动灵敏度对应 对于在图案边缘变化时要设置的适当曝光剂量和曝光剂量之间的差异，基于计算出的边缘移动灵敏度确定掩模图案的监视部分，实际在掩模基板上形成掩模图案，获取 基于所获取的尺寸，确定在掩模基板上形成的掩模图案的评估值，并且确定评估值是否满足的掩模图案的形成在掩模基板上的对应于监视部分的掩模图案的部分中的图案的尺寸 预定条件。
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公开(公告)号：US20060077702A1
公开(公告)日：2006-04-13
申请号：US11125274
申请日：2005-05-10
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C16/0408 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531
摘要： Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AAi, AAi+1, . . . , AAn, which extend on a memory cell array along the column length; a plurality of word line patterns WL1, WL2, . . . , extend along the row length and are non-uniformly arranged; a plurality of select gate line patterns SG1, SG2, . . . , are arranged parallel to the plurality of word line patterns; borderless contacts are formed near the ends of the word line patterns on the memory cell array, and are in contact with part of an interconnect extended from the end of the memory cell array, but are not in contact with interconnects adjacent to that interconnect; and bit line contacts are formed within contact forming regions provided by removing part of the plurality of word line patterns and select gate line patterns through double exposure.
摘要翻译： 用于字线的无边界触点或通过位线的触点使用互连图案形成，其中一部分被去除。 半导体存储器包括：多个有源区域AA 1，A 2，...，N 1，...， 。 。 ，沿着列长延伸在存储单元阵列上的AA 多个字线图形WL 1，WL 2，...。 。 。 沿着行长延伸并且不均匀地布置; 多个选择栅极线图案SG 1，SG 2，...。 。 。 被平行于所述多个字线图形排列; 在存储单元阵列上的字线图案的端部附近形成无边界触点，并且与从存储单元阵列的端部延伸的互连部分接触，但不与与该互连件相邻的互连件接触; 并且通过去除多个字线图案的一部分而提供的接触形成区域内形成位线接触，并通过双重曝光选择栅极线图案。
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公开(公告)号：US20060064191A1
公开(公告)日：2006-03-23
申请号：US10545658
申请日：2003-09-17
IPC分类号： G06F19/00
CPC分类号： H01L23/544 , G05B19/4183 , G05B2219/31304 , G05B2219/45031 , H01L21/67276 , H01L21/67294 , H01L2223/5442 , H01L2223/54433 , H01L2223/5444 , H01L2924/0002 , Y02P90/04 , Y02P90/10 , H01L2924/00
摘要： The present invention provides a semiconductor device furnished with tamper-resistant identification information by forming a circuit pattern 2B which differs from one semiconductor chip to another in a semiconductor chip 2 packaged in a semiconductor device 1 in addition to an original circuit pattern 2A and expressing the identification information by this circuit pattern 2B and the invention further provides a semiconductor manufacturing management system targeted at a product mounted with this semiconductor device, capable of managing the product from the manufacturing to the mode of use of the semiconductor device.
摘要翻译： 本发明提供了一种半导体器件，其通过在除了原始电路图案2A和半导体器件1之外的半导体器件1中封装的半导体芯片2中形成不同于一个半导体芯片的电路图案2B而配备防篡改识别信息，以及 通过该电路图案2B表示识别信息，并且本发明还提供了一种针对安装有该半导体器件的产品的半导体制造管理系统，其能够管理从半导体器件的制造到使用模式的产品。
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公开(公告)号：US20050183705A1
公开(公告)日：2005-08-25
申请号：US11059504
申请日：2005-02-17
申请人： Kunio Nanba , Kazuto Maeda , Koji Hashimoto , Tatsuo Sakai
发明人： Kunio Nanba , Kazuto Maeda , Koji Hashimoto , Tatsuo Sakai
CPC分类号： F02D9/1045 , F02M26/50 , F02M26/54 , F02M26/70 , F02M26/73
摘要： Emission gas recycling equipment includes a passage for recycling a part of an emission gas and a control valve for controlling an amount of the part of the emission gas. The control valve includes: a housing having a pipe portion; a butterfly valve accommodated in the pipe portion rotatable in a first direction and a second direction; a seal ring for sealing a clearance; and valve open/close operation means for stopping the butterfly valve at the valve full close position after the valve open/close operation means operates the butterfly valve to open and to close equal to or more than one cycle across the valve full close position at the time when the engine stops or after the engine stops.
摘要翻译： 排放气体回收设备包括用于回收一部分排放气体的通道和用于控制排出气体的一部分量的控制阀。 控制阀包括：具有管部分的壳体; 容纳在沿第一方向和第二方向旋转的管部中的蝶阀; 用于密封间隙的密封环; 以及阀打开/关闭操作装置，用于在阀打开/关闭操作装置操作蝶阀以打开和关闭等于或大于一个循环的阀完全关闭位置时将蝶阀停止在阀完全关闭位置 发动机停止或发动机停止后的时间。
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77.发明申请Carrier for gene detection and its use for detecting validity of interferon therapy 审中-公开用于基因检测的载体及其用于检测干扰素治疗有效性的用途公开(公告)号：US20050100909A1
公开(公告)日：2005-05-12
申请号：US10633659
申请日：2003-08-05
申请人： Minako Hijikata , Shunji Mishiro , Yasuhiko Oota , Koji Hashimoto
发明人： Minako Hijikata , Shunji Mishiro , Yasuhiko Oota , Koji Hashimoto
IPC分类号： G01N33/53 , C12M1/00 , C12M1/34 , C12N15/09 , C12Q1/68 , C12Q1/70 , C40B40/06 , C40B40/10 , C40B60/14 , G01N37/00
CPC分类号： B82Y30/00 , B01J2219/00378 , B01J2219/00497 , B01J2219/00527 , B01J2219/00585 , B01J2219/00596 , B01J2219/00653 , B01J2219/00657 , B01J2219/00677 , B01J2219/00707 , B01J2219/00713 , B01J2219/00722 , B01J2219/00725 , C12Q1/6837 , C12Q1/6883 , C12Q1/6886 , C12Q1/707 , C12Q2600/106 , C12Q2600/156 , C40B40/06 , C40B40/10 , C40B60/14 , C12Q2565/607
摘要： A carrier for gene detection as a means for prediction before treatment whether interferon therapy is valid or not for a patient, a method for detection of interferon therapy for an individual, an apparatus for gene detection, and a kit for detection of validity of interferon therapy.
摘要翻译： 用于基因检测的载体作为治疗前预测的手段，干扰素治疗对于患者是否有效，用于检测个体的干扰素治疗的方法，用于基因检测的装置和用于检测干扰素治疗有效性的试剂盒 。
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公开(公告)号：US20050099847A1
公开(公告)日：2005-05-12
申请号：US11008531
申请日：2004-12-10
申请人： Masayuki Ichige , Koji Hashimoto , Tatsuaki Kuji , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Koji Sakui
发明人： Masayuki Ichige , Koji Hashimoto , Tatsuaki Kuji , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Koji Sakui
IPC分类号： G11C16/00 , G06K17/00 , G06K19/077 , G11C11/34 , G11C14/00 , G11C16/02 , G11C16/04 , G11C16/06 , H01L21/82 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11524
摘要： A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.
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公开(公告)号：US20050095637A1
公开(公告)日：2005-05-05
申请号：US10991427
申请日：2004-11-19
IPC分类号： C40B40/06 , G01N27/403 , C12Q1/68 , C12M1/34
CPC分类号： C12Q1/6825 , B01J2219/00608 , B01J2219/0061 , B01J2219/00612 , B01J2219/00621 , B01J2219/00626 , B01J2219/0063 , B01J2219/00637 , B01J2219/00653 , B01J2219/00722 , C40B40/06 , G01N27/3276 , C12Q2565/607
摘要： A nucleic acid detection sensor comprises a plurality of nucleic acid chain fixed electrodes to which a probe nucleic acid chain is fixed, and a counter electrode which is arranged opposite to the nucleic acid chain fixed electrode, and a current flowing between the counter electrode and the nucleic acid chain fixed electrode.
摘要翻译： 核酸检测传感器包括固定探针核酸链的多个核酸链固定电极和与核酸链固定电极相对配置的对电极和在对电极和对置电极之间流动的电流 核酸链固定电极。
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80.发明申请公开(公告)号：US20050003305A1
公开(公告)日：2005-01-06
申请号：US10832995
申请日：2004-04-28
申请人： Koji Hashimoto , Tadahito Fujisawa , Yuko Kono , Takashi Obara
发明人： Koji Hashimoto , Tadahito Fujisawa , Yuko Kono , Takashi Obara
摘要： A photo mask formed with patterns to be transferred to a substrate using an exposure apparatus, the photo mask comprising a pattern row having three or more hole patterns surrounded by a shielding portion or a semitransparent film and arranged along one direction, and an assist pattern surrounded by the shielding portion or semitransparent film and having a longitudinal direction and a latitudinal direction, the assist pattern being located at a specified distance from the pattern row in a direction orthogonal to the one direction, the longitudinal direction of the assist pattern being substantially parallel with the one direction, the longitudinal length of the assist pattern being equivalent to or larger than the longitudinal length of the pattern row, the assist pattern being not transferred to the substrate.
摘要翻译： 一种光掩模，其形成有使用曝光装置转印到基板的图案，所述光掩模包括具有由屏蔽部分或半透明膜围绕并沿着一个方向布置的三个或更多孔图案的图案行和辅助图案包围 通过屏蔽部分或半透明膜并具有纵向方向和纬度方向，辅助图案位于与图案行在与该一个方向正交的方向上特定距离处，辅助图案的纵向方向基本上平行于 一个方向，辅助图案的纵向长度等于或大于图案行的纵向长度，辅助图案不被转印到基底。
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