公开(公告)号：US20180123035A1

公开(公告)日：2018-05-03

申请号：US15857448

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Scott E. Sills ,  John K. Zahurak

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/085 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1675

Abstract: Some embodiments include methods of forming memory cells. A series of rails is formed to include bottom electrode contact material. Sacrificial material is patterned into a series of lines that cross the series of rails. A pattern of the series of lines is transferred into the bottom electrode contact material. At least a portion of the sacrificial material is subsequently replaced with top electrode material. Some embodiments include memory arrays that contain a second series of electrically conductive lines crossing a first series of electrically conductive lines. Memory cells are at locations where the electrically conductive lines of the second series overlap the electrically conductive lines of the first series. First and second memory cell materials are within the memory cell locations. The first memory cell material is configured as planar sheets and the second memory cell material is configured as upwardly-opening containers.

公开(公告)号：US09960114B1

公开(公告)日：2018-05-01

申请号：US15585396

申请日：2017-05-03

Applicant: Micron Technology, Inc.

Inventor： Sourabh Dhir ,  Andrew L. Li ,  Sanh D. Tang ,  Naoyoshi Kobayashi ,  Katsumi Koge

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76837 ,  H01L27/10814 ,  H01L27/10885

Abstract: A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.0 is formed laterally outward of opposing sides of the first insulator material in the vertical cross-section. Additional method aspects, including structure independent of method of fabrication, are disclosed.

公开(公告)号：US09754953B2

公开(公告)日：2017-09-05

申请号：US14987370

申请日：2016-01-04

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak

IPC: H01L29/788 ,  H01L27/11556 ,  H01L29/792 ,  H01L21/28 ,  H01L27/11582 ,  H01L27/11578 ,  H01L27/11524 ,  H01L27/11521 ,  H01L29/04 ,  H01L29/167 ,  H01L29/49

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/167 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926

Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.

公开(公告)号：US09564442B2

公开(公告)日：2017-02-07

申请号：US14681884

申请日：2015-04-08

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Wolfgang Mueller ,  Sourabh Dhir ,  Dylan R. MacMaster

IPC: H01L21/8238 ,  H01L27/108 ,  H01L21/768 ,  H01L21/311 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L23/528

CPC classification number: H01L27/10805 ,  H01L21/02068 ,  H01L21/31111 ,  H01L21/743 ,  H01L21/762 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/528 ,  H01L27/10808 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/0649 ,  H01L29/7391

Abstract: A method of forming contacts for a semiconductor device structure comprises forming contact holes extending into neighboring semiconductive pillars and into a nitride material of nitride-capped electrodes. Composite structures are formed within the contact holes and comprise oxide structures over sidewalls of the contact holes and nitride structures over the oxide structures. Conductive structures are formed over inner sidewalls of the composite structures. Additional nitride-capped electrodes are formed over the conductive structures and extend perpendicular to the nitride-capped electrodes. Pairs of nitride spacers are formed over opposing sidewalls of the additional nitride-capped electrodes and are separated from neighboring pairs of nitride spacers by apertures extending to upper surfaces of a portion of the neighboring semiconductive pillars. Portions of the oxide structures are removed to expose sidewalls of the portion of the neighboring semiconductive pillars. Semiconductor device structures and additional methods are also described.

Abstract translation: 形成用于半导体器件结构的触点的方法包括形成延伸到相邻的半导体柱中的接触孔，并形成氮化物覆盖的电极的氮化物材料。 复合结构形成在接触孔内并且包括在接触孔的侧壁上的氧化物结构和氧化物结构上的氮化物结构。 导电结构形成在复合结构的内侧壁上。 附加的氮化物封盖的电极形成在导电结构之上并垂直于氮化物封盖的电极延伸。 一对氮化物间隔物形成在另外的氮化物覆盖的电极的相对侧壁上，并且通过延伸到相邻半导体柱的一部分的上表面的孔与相邻的氮化物间隔物相分离。 去除部分氧化物结构以暴露相邻半导体柱的部分的侧壁。 还描述了半导体器件结构和附加方法。

公开(公告)号：US20170025517A1

公开(公告)日：2017-01-26

申请号：US15284017

申请日：2016-10-03

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak ,  Michael P. Violette

IPC: H01L29/66 ,  H01L27/102 ,  H01L29/74 ,  H01L29/423

CPC classification number: H01L29/66363 ,  H01L27/1027 ,  H01L29/42308 ,  H01L29/74 ,  H01L2924/1301

Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.

Abstract translation: 显示存储器件和制造存储器件的方法。 所示的方法和配置提供用于增加存储器密度的折叠和垂直存储器件。 提供的方法减少了对诸如深掺杂剂植入物的制造方法的需要。

公开(公告)号：US20160336325A1

公开(公告)日：2016-11-17

申请号：US15218487

申请日：2016-07-25

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Wolfgang Mueller ,  Brent Gilgen ,  Dylan R. Macmaster ,  Jim A. Jozwiak

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L27/108 ,  H01L21/32133 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/90

Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.

公开(公告)号：US09373715B2

公开(公告)日：2016-06-21

申请号：US14075480

申请日：2013-11-08

Applicant: Micron Technology, Inc.

Inventor： Wolfgang Mueller ,  Sanh D. Tang ,  Sourabh Dhir ,  Srinivas Pulugurtha

IPC: H01L29/78 ,  G11C11/40 ,  H01L27/02 ,  H01L27/105 ,  H01L29/66 ,  H01L27/108

CPC classification number: H01L29/7827 ,  G11C11/40 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666

Abstract: A semiconductor device may include a memory array including vertical memory cells connected to a digit line, word lines, and a body connection line. A row or column of the memory array may include one or more pillars connected to the body connection line. A voltage may be applied to the body connection line through at least one pillar connected to the body connection line. Application of the voltage to the body connection line may reduce floating body effects. Methods of forming a connection between at least one pillar and a voltage supply are disclosed. Semiconductor devices including such connections are also disclosed.

Abstract translation: 半导体器件可以包括存储器阵列，其包括连接到数字线，字线和主体连接线的垂直存储器单元。 存储器阵列的行或列可以包括连接到主体连接线的一个或多个支柱。 可以通过连接到主体连接线的至少一个支柱将电压施加到主体连接线。 施加电压到身体连接线可能会减少浮体效应。 公开了形成至少一个柱和电压源之间的连接的方法。 还公开了包括这种连接的半导体器件。

公开(公告)号：US09318430B2

公开(公告)日：2016-04-19

申请号：US14602559

申请日：2015-01-22

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC: H01L23/52 ,  H01L27/10

CPC classification number: H01L27/11582 ,  G11C13/0007 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L23/52 ,  H01L23/528 ,  H01L27/10 ,  H01L27/101 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/249 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.

Abstract translation: 形成电路部件的方法包括形成水平延伸和垂直重叠特征的堆叠。 堆叠具有主要部分和端部。 至少一些特征在末端部分中更深地移动到堆叠中的端部中在水平方向上延伸得更远。 操作结构通过主要部分的特征垂直地形成，并且虚拟结构通过端部中的特征垂直地形成。 通过特征形成水平细长的开口以从特征的材料形成水平细长的和垂直重叠的线。 这些线分别从主要部分延伸到端部，并且单独地横向地围绕操作结构和虚拟结构的垂直延伸部分的侧面。 至少部分地，在水平伸长的开口之间的主要端部和端部中部分地去除在线之间高度的牺牲材料。 公开了其他方面和实现。

公开(公告)号：US20150333257A1

公开(公告)日：2015-11-19

申请号：US14806259

申请日：2015-07-22

Applicant: Micron Technology, Inc.

Inventor： D.V. Nirmal Ramaswamy ,  Sanh D. Tang ,  Alessandro Torsi ,  Muralikrishnan Balakrishnan ,  Xiaonan Chen ,  John K. Zahurak

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/1641

Abstract: A method of forming a resistive memory element comprises forming an oxide material over a first electrode. The oxide material is exposed to a plasma process to form a treated oxide material. A second electrode is formed on the treated oxide material. Additional methods of forming a resistive memory element, as well as related resistive memory elements, resistive memory cells, and resistive memory devices are also described.

Abstract translation: 形成电阻式存储元件的方法包括在第一电极上形成氧化物材料。 将氧化物材料暴露于等离子体工艺以形成经处理的氧化物材料。 在经处理​​的氧化物材料上形成第二电极。 还描述了形成电阻性存储器元件以及相关的电阻性存储器元件，电阻存储器单元和电阻存储器件的附加方法。

公开(公告)号：US08995193B2

公开(公告)日：2015-03-31

申请号：US14101041

申请日：2013-12-09

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang

IPC: G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L27/11524 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include NAND memory constructions. The constructions may contain semiconductor material pillars extending upwardly between dielectric regions, with individual pillars having a pair of opposing vertically-extending sides along a cross-section. First conductivity type regions may be along first sides of the pillars, and second conductivity type regions may be along second sides of the individual pillars; with the second conductivity type regions contacting interconnect lines. Vertical NAND strings may be over the pillars, and select devices may selectively couple the NAND strings with the interconnect lines. The select devices may have vertical channels directly against the semiconductor material pillars and directly against upper regions of the first and second conductivity type regions. Some embodiments include methods of forming NAND memory constructions.

Abstract translation: 一些实施例包括NAND存储器结构。 这些结构可以包含在电介质区域之间向上延伸的半导体材料柱，其中单独的柱具有沿着横截面的一对相对的垂直延伸的侧面。 第一导电类型区域可以沿着柱的第一侧，并且第二导电类型区域可以沿着各个柱的第二侧; 第二导电类型区域接触互连线。 垂直NAND串可以在柱上，并且选择装置可以选择性地将NAND串与互连线耦合。 选择装置可以具有直接抵靠半导体材料柱的垂直通道并且直接抵靠第一和第二导电类型区域的上部区域。 一些实施例包括形成NAND存储器结构的方法。