摘要:
Provided are cleaning methods and systems to remove unintended metallic deposits from electroplating apparatuses using reverse current deplating techniques. Such cleaning involves positioning a cleaning (deplating) disk in an electroplating cup similar to a regular processed substrate. The front surface of the cleaning disk includes a corrosion resistant conductive material to form electrical connections to deposits on the cup's surfaces. The disk is sealed in the cup and submerged into a plating solution. A reverse current is then applied to the front conductive surface of the disk to initiate deplating of the deposits. Sealing compression in the cup may change during cleaning to cause different deformation of the lip seal and to form new electrical connections to the deposits. The proposed cleaning may be applied to remove deposits formed during electroplating of alloys, in particular, tin-silver alloys widely used for semiconductor and wafer level packaging.
摘要:
Methods and apparatus are provided for processing semiconductor wafers sequentially. Sequential processes employ multi-station processing modules, where particular encompassing wafer processes are divided into sub-processes, each optimized for increasing wafer to wafer uniformity, result quality, and overall wafer throughput. In one example, a copper electroplating module includes separate stations for wetting, initiation, seed layer repair, fill, overburden, reclaim, and rinse.
摘要:
Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.
摘要:
Described are apparatus and methods for electroplating one or more metals onto a substrate. Embodiments include electroplating apparatus configured for, and methods including, efficient mass transfer during plating so that highly uniform plating layers are obtained. In specific embodiments, the mass transfer is achieved using a combination of impinging flow and shear flow at the wafer surface.
摘要:
Provided are methods and apparatuses for depositing barrier layers for blocking diffusion of conductive materials from conductive lines into dielectric materials in integrated circuits. The barrier layer may contain copper. In some embodiments, the layers have conductivity sufficient for direct electroplating of conductive materials without needing intermediate seed layers. Such barrier layers may be used with circuits lines that are less than 65 nm wide and, in certain embodiments, less than 40 nm wide. The barrier layer may be passivated to form easily removable layers including sulfides, selenides, and/or tellurides of the materials in the layer.
摘要:
Disclosed are pre-wetting apparatus designs and methods. These apparatus designs and methods are used to pre-wet a wafer prior to plating a metal on the surface of the wafer. Disclosed compositions of the pre-wetting fluid prevent corrosion of a seed layer on the wafer and also improve the filling rates of features on the wafer.
摘要:
Chemical etching methods and associated modules for performing the removal of metal from the edge bevel region of a semiconductor wafer are described. The methods and systems provide the thin layer of pre-rinsing liquid before applying etchant at the edge bevel region of the wafer. The etchant is less diluted and diffuses faster through a thinned layer of rinsing liquid. An edge bevel removal embodiment involving that is particularly effective at reducing process time, narrowing the metal taper and allowing for subsequent chemical mechanical polishing, is disclosed.
摘要:
A substantially uniform layer of a metal is electroplated onto a work piece having a seed layer thereon. This is accomplished by employing a “high resistance ionic current source,” which solves the terminal problem by placing a highly resistive membrane (e.g., a microporous ceramic or fretted glass element) in close proximity to the wafer, thereby swamping the system's resistance. The membrane thereby approximates a constant current source. By keeping the wafer close to the membrane surface, the ionic resistance from the top of the membrane to the surface is much less than the ionic path resistance to the wafer edge, substantially compensating for the sheet resistance in the thin metal film and directing additional current over the center and middle of the wafer.
摘要:
An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting. After the metal regions are etched and recessed in the substrate surface, a conductive capping layer is formed using electroless deposition over the recessed exposed metal regions.