公开(公告)号：US09543211B1

公开(公告)日：2017-01-10

申请号：US14864881

申请日：2015-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Yu-Cheng Tung ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  En-Chiuan Liou ,  Wei-Hao Huang ,  Chih-Sen Huang ,  Ching-Wen Hung

IPC: H01L21/70 ,  H01L21/8234 ,  H01L21/283 ,  H01L27/088

CPC classification number: H01L21/823437 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L27/088

Abstract: A manufacturing method of a semiconductor structure includes the following steps. Gate structures are formed on a semiconductor substrate. A source/drain contact is formed between two adjacent gate structures. The source/drain contact is recessed by a recessing process. A top surface of the source/drain contact is lower than a top surface of the gate structure after the recessing process. A stop layer is formed on the gate structures and the source/drain contact after the recessing process. A top surface of the stop layer on the source/drain contact is lower than the top surface of the gate structure. A semiconductor structure includes the semiconductor substrate, the gate structures, a gate contact structure, and the source/drain contact. The source/drain contact is disposed between two adjacent gate structures, and the top surface of the source/drain contact is lower than the top surface of the gate structure.

Abstract translation: 半导体结构的制造方法包括以下步骤。 栅极结构形成在半导体衬底上。 在两个相邻栅极结构之间形成源极/漏极接触。 源极/漏极接触器通过凹陷工艺凹陷。 源极/漏极接触件的顶表面在凹陷过程之后低于栅极结构的顶表面。 在凹陷过程之后，在栅极结构和源极/漏极触点上形成阻挡层。 源极/漏极接触点上的阻挡层的顶表面低于栅极结构的顶表面。 半导体结构包括半导体衬底，栅极结构，栅极接触结构和源极/漏极接触。 源极/漏极触点设置在两个相邻的栅极结构之间，源极/漏极接触的顶表面低于栅极结构的顶部表面。

公开(公告)号：US20170005181A1

公开(公告)日：2017-01-05

申请号：US14820565

申请日：2015-08-07

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/283 ,  H01L21/308 ,  H01L21/31 ,  H01L21/762 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L21/283 ,  H01L21/308 ,  H01L21/31 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/845

Abstract: A semiconductor device includes first fin-shaped structures and second fin-shaped structures, which are separately disposed on a semiconductor substrate. Each of the first and second fin-shaped structures includes a base portion and a top portion protruding from the top portion. The base portions of the second fin-shaped structures are wider than the top portions of the second fin-shaped structures, and the top portions of the second fin-shaped structures are as wide as the top portions of the first fin-shaped structures. Each second fin-shaped structure further includes a recessed region on its sidewall.

Abstract translation: 半导体器件包括分开设置在半导体衬底上的第一鳍状结构和第二鳍状结构。 第一和第二鳍状结构中的每一个包括基部和从顶部突出的顶部。 第二鳍状结构的基部比第二鳍状结构的顶部宽，并且第二鳍状结构的顶部与第一鳍状结构的顶部一样宽。 每个第二鳍状结构还包括在其侧壁上的凹陷区域。

公开(公告)号：US20170005008A1

公开(公告)日：2017-01-05

申请号：US14814516

申请日：2015-07-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chao-Hung Lin ,  Yu-Cheng Tung

IPC: H01L21/8234 ,  H01L29/06 ,  H01L21/308 ,  H01L21/28 ,  H01L21/762 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/28123 ,  H01L21/3086 ,  H01L21/762 ,  H01L21/76232 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

Abstract: A method for fabricating a semiconductor device having a gate structure includes forming a substrate including at least two fin structures protruding from a top surface of the substrate, the substrate including a first recess and a second recess disposed under the first recess, and the first recess and the second recess being disposed between the fin structures, wherein a width of the first recess is larger than a width of the second recess, and the first recess and the second recess form a step structure; forming an insulating structure in the second recess; and forming the gate structure on the insulating structure, wherein the first recess and the second recess are filled up with the gate structure and the insulating structure.

Abstract translation: 一种用于制造具有栅极结构的半导体器件的方法，包括形成包括至少两个鳍状结构的衬底，所述鳍结构从衬底的顶表面突出，所述衬底包括第一凹部和设置在第一凹部下方的第二凹部， 并且所述第二凹部设置在所述翅片结构之间，其中所述第一凹部的宽度大于所述第二凹部的宽度，并且所述第一凹部和所述第二凹部形成台阶结构; 在所述第二凹部中形成绝缘结构; 以及在所述绝缘结构上形成所述栅极结构，其中所述第一凹槽和所述第二凹槽被所述栅极结构和所述绝缘结构填充。

公开(公告)号：US20160315171A1

公开(公告)日：2016-10-27

申请号：US14727853

申请日：2015-06-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chao-Hung Lin ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Jun-Jie Wang ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Hung-Chan Lin ,  Yu-Hsiang Lin

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653

Abstract: A method for manufacturing a semiconductor device having a metal gate includes forming a filling layer and a high-K gate dielectric layer in the first recess between a pair of spacers, wherein the high-K gate dielectric layer and the filling layer are stacked in the first recess sequentially, and an exposed top surface of the high-K gate dielectric layer and a top surface of the filling layer are lower than a top surface of each spacer; and removing a part of each spacer and widening the first recess on the top surface of the filling layer to form a second recess, wherein a width of the second recess is larger than a width of the first recess.

Abstract translation: 一种具有金属栅极的半导体器件的制造方法包括在一对间隔物之间​​的第一凹部中形成填充层和高K栅极电介质层，其中高K栅极介电层和填充层堆叠在 第一凹部，高K栅极电介质层的露出顶表面和填充层的顶表面比每个间隔物的顶表面低; 并且移除每个间隔物的一部分并加宽填充层的顶表面上的第一凹部以形成第二凹部，其中第二凹部的宽度大于第一凹部的宽度。

公开(公告)号：US20160313652A1

公开(公告)日：2016-10-27

申请号：US14696488

申请日：2015-04-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chia-Ching Lin ,  Yi-Jing Wang

IPC: G03F7/20 ,  G03F1/70

CPC classification number: G03F7/70633 ,  G03F1/70

Abstract: An overlay operation method and an overlay control method are disclosed. A first mark and a second mark are identified on a substrate, wherein the first mark and the second mark are formed by a process in combination with using a photomask. Next, a first measurement is performed to obtain an offset between the first mark and the second mark in a direction. Then, an operation is performed to judge whether the offset is in a range from a pre-determined offset minus a deviation to the pre-determined offset plus the deviation, wherein the pre-determined offset is determined by the photomask.

Abstract translation: 公开了覆盖操作方法和覆盖控制方法。 在基板上识别第一标记和第二标记，其中第一标记和第二标记通过与使用光掩模组合的方法形成。 接下来，执行第一测量以在方向上获得第一标记和第二标记之间的偏移。 然后，执行操作以判断偏移是否在从预定偏移减去偏差到预定偏移加上偏差的范围内，其中预定偏移由光掩模确定。

公开(公告)号：US20160313648A1

公开(公告)日：2016-10-27

申请号：US14692761

申请日：2015-04-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou

IPC: G03F7/20 ,  H01L23/544 ,  H01L21/265 ,  H01L21/324 ,  H01L21/02 ,  H01L21/66 ,  H01L21/308

CPC classification number: H01L23/544 ,  G03F7/70633 ,  H01L22/12 ,  H01L22/20 ,  H01L22/26

Abstract: A monitor method for process control in a semiconductor fabrication process is disclosed. A first alignment mark is formed in a layer on a substrate, and its position is measured and stored in a first measurement data. A fabrication process is then performed. Afterwards, another measurement is performed to measure the position of the first alignment mark and to generate a second measurement data. Finally, an offset value between the position of the first alignment mark in the first measurement data and those in the second measurement data is calculated.

Abstract translation: 公开了一种半导体制造工艺中的工艺控制的监视方法。 第一对准标记形成在基板上的层中，并且其位置被测量并存储在第一测量数据中。 然后执行制造过程。 之后进行另一测量来测量第一对准标记的位置并产生第二测量数据。 最后，计算第一测量数据中的第一对准标记的位置与第二测量数据中的第一对准标记的位置之间的偏移值。

公开(公告)号：US20160307850A1

公开(公告)日：2016-10-20

申请号：US14687912

申请日：2015-04-15

Applicant: United Microelectronics Corp.

Inventor： Chia-Ching Lin ,  En-Chiuan Liou ,  Chia-Hung Wang ,  Sho-Shen Lee

IPC: H01L23/544 ,  H01L29/78

CPC classification number: H01L29/785 ,  G03F7/70633 ,  G03F7/70683

Abstract: An overlay mark for determining the alignment between two separately generated patterns formed along with two successive layers above a substrate is provided in the present invention, wherein both the substrate and the overlay mark include at least two pattern zones having periodic structures with different orientations, and the periodic structures of the overlay mark are orthogonally overlapped with the periodic structures of the substrate.

Abstract translation: 在本发明中提供了用于确定在衬底上方与两个连续层形成的两个单独产生的图案之间的对准的覆盖标记，其中衬底和覆盖标记都包括具有不同取向的周期性结构的至少两个图案区域，以及 覆盖标记的周期性结构与衬底的周期性结构正交地重叠。

公开(公告)号：US20160240629A1

公开(公告)日：2016-08-18

申请号：US14621358

申请日：2015-02-12

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L21/321 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/32139 ,  H01L29/6653 ,  H01L29/66553

Abstract: A semiconductor process for forming gates with different pitches includes the following steps. A gate layer is formed on a substrate. A first mandrel and a second mandrel are respectively formed on the gate layer. A first spacer material is formed to conformally cover the first mandrel but exposing the second mandrel. A second spacer material is formed to conformally cover the first spacer material and the second mandrel. The first spacer material and the second spacer material are etched to form a first spacer beside the first mandrel and a second spacer beside the second mandrel simultaneously. The first mandrel and the second mandrel are removed. Layouts of the first spacer and the second spacer are transferred to the gate layer, thereby a first gate and a second gate being formed. Moreover, a semiconductor process, which forms the first spacer and the second spacer separately, is also provided.

Abstract translation: 用于形成具有不同间距的门的半导体工艺包括以下步骤。 栅极层形成在基板上。 第一心轴和第二心轴分别形成在栅极层上。 形成第一间隔材料以保形地覆盖第一心轴但暴露第二心轴。 形成第二间隔材料以共形地覆盖第一间隔物材料和第二心轴。 蚀刻第一间隔物材料和第二间隔物材料以在第一心轴旁边形成第一间隔物，同时在第二心轴旁边形成第二间隔物。 去除第一心轴和第二心轴。 第一间隔物和第二间隔物的布置被转移到栅极层，从而形成第一栅极和第二栅极。 此外，还提供了分别形成第一间隔件和第二间隔件的半导体工艺。

公开(公告)号：US20160233301A1

公开(公告)日：2016-08-11

申请号：US14663464

申请日：2015-03-20

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/324 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02667 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present invention provides a semiconductor structure, including a substrate, a first nanowire structure disposed on the substrate, and the first nanowire structure includes a gate region and a source/drain region The diameter of the first nanowire structure within the gate region is different from the diameter of the first nanowire structure within the source/drain region.

Abstract translation: 本发明提供一种半导体结构，包括基板，设置在基板上的第一纳米线结构，第一纳米线结构包括栅极区域和源极/漏极区域。栅极区域内的第一纳米线结构的直径不同于 源极/漏极区域内的第一纳米线结构的直径。

公开(公告)号：US09400435B2

公开(公告)日：2016-07-26

申请号：US14457136

申请日：2014-08-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chia-Chang Hsu ,  Teng-Chin Kuo ,  Chia-Hung Wang ,  Tuan-Yen Yu ,  Yuan-Chi Pai ,  Chun-Chi Yu

IPC: G03F7/20 ,  G03F9/00 ,  G05B19/18 ,  G03F1/42

CPC classification number: G03F7/70633 ,  G03F1/42 ,  G03F7/70491 ,  G05B19/188 ,  G05B2219/45027 ,  G05B2219/45031

Abstract: A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.

Abstract translation: 校正重叠错误的方法包括以下步骤。 首先，捕获设置在基板上的覆盖标记，以生成重叠标记信息。 覆盖标记包括至少一对第一标记图案和至少第一标记图案上方的第二标记图案。 然后，计算叠加标记信息以产生两个第一标记图案之间的偏移值，并产生第二标记图案与第一标记图案之一之间的偏移值。 最后，偏移值用于补偿偏移值，以产生修正的移位值。