公开(公告)号：US09495107B2

公开(公告)日：2016-11-15

申请号：US14547663

申请日：2014-11-19

Applicant: International Business Machines Corporation

Inventor： Timothy C. Bronson ,  Garrett M. Drapala ,  Mark S. Farrell ,  Hieu T. Huynh ,  William J. Lewis ,  Pak-Kin Mak ,  Craig R. Walters

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0617 ,  G06F3/065 ,  G06F3/0664 ,  G06F3/0683 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0837 ,  G06F12/0842 ,  G06F2212/1041 ,  G06F2212/283 ,  G06F2212/608

Abstract: A computing device is provided and includes a first physical memory device, a second physical memory device and a hypervisor configured to assign resources of the first and second physical memory devices to a logical partition. The hypervisor configures a dynamic memory relocation (DMR) mechanism to move entire storage increments currently processed by the logical partition between the first and second physical memory devices in a manner that is substantially transparent to the logical partition.

Abstract translation: 提供了一种计算设备，并且包括第一物理存储器设备，第二物理存储器设备和管理程序，其被配置为将第一和第二物理存储器设备的资源分配给逻辑分区。 管理程序配置动态存储器重定位（DMR）机制以使逻辑分区当前处理的整个存储增量以对逻辑分区基本透明的方式移动在第一和第二物理存储器设备之间。

公开(公告)号：US20160328323A1

公开(公告)日：2016-11-10

申请号：US15210962

申请日：2016-07-15

Applicant: International Business Machines Corporation

Inventor： David M. Daly ,  Vijayalakshmi Srinivasan

IPC: G06F12/0815

CPC classification number: G06F12/0815 ,  G06F3/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/084 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1048 ,  G06F2212/151 ,  G06F2212/251 ,  G06F2212/283 ,  G06F2212/608 ,  G06F2212/621

Abstract: A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.

Abstract translation: 在多处理器系统中提供用于存储器相干性的机制。 响应于来自多处理器系统的处理核心的存储器操作导致高速缓存未命中，该机制检查与处理核心相关联的专用区域表。 存储器操作尝试访问存储器区域。 响应于确定存储器区域对应于专用区域表中的条目，该机制执行远程存储器控制器的远程存储器控制器窥探器而不窥探多处理器系统。

公开(公告)号：US09477607B2

公开(公告)日：2016-10-25

申请号：US14930464

申请日：2015-11-02

Applicant: International Business Machines Corporation

Inventor： Michael T. Benhase ,  Lokesh M. Gupta ,  Joseph S. Hyde, II ,  Lee C. LaFrese

IPC: G06F12/08 ,  G06F3/06 ,  G06F12/02 ,  G06F12/12

CPC classification number: G06F12/0868 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0873 ,  G06F12/0888 ,  G06F12/122 ,  G06F12/123 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/202 ,  G06F2212/312 ,  G06F2212/313 ,  G06F2212/604 ,  G06F2212/608 ,  G06F2212/7208

Abstract: A storage controller receives a request that corresponds to an access of a track. A determination is made as to whether the track corresponds to data stored in a solid state disk. Record staging to a cache from the solid state disk is performed, in response to determining that the track corresponds to data stored in the solid state disk, wherein each track is comprised of a plurality of records.

公开(公告)号：US20160306747A1

公开(公告)日：2016-10-20

申请号：US15196093

申请日：2016-06-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael K. Gschwind

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/1045 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/065 ,  G06F3/0656 ,  G06F3/0664 ,  G06F3/0673 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3851 ,  G06F12/0808 ,  G06F12/0833 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/1009 ,  G06F12/128 ,  G06F2212/1008 ,  G06F2212/152 ,  G06F2212/452 ,  G06F2212/608 ,  G06F2212/62 ,  G06F2212/657 ,  G06F2212/682 ,  G06F2212/683 ,  G06F2212/70

Abstract: A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page table entries). A synchronization instruction is used that ensures after the instruction has completed that updates to the cached entries that occurred prior to the synchronization instruction are made visible in memory. Synchronization may be used to facilitate memory management operations, such as bulk operations used to change a large section of memory to read-only, operations to manage a free list of memory pages, and/or operations associated with terminating processes.

公开(公告)号：US09471504B2

公开(公告)日：2016-10-18

申请号：US15155493

申请日：2016-05-16

Applicant: International Business Machines Corporation

Inventor： Khary J. Alexander ,  Jonathan T. Hsieh ,  Christian Jacobi ,  James R. Mitchell

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0877 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/3834 ,  G06F12/0806 ,  G06F12/0833 ,  G06F12/0842 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/12 ,  G06F12/128 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/214 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/6026 ,  G06F2212/608 ,  G06F2212/62 ,  G06F2212/621

Abstract: A load request is received to retrieve a piece of data from a location in memory and the load request follows one or more store requests in a set of instructions to store a piece of data in the location in memory. One or more possible locations in a cache for a piece of data corresponding to the location in memory is determined. Each possible location of the one or more possible locations in the cache is determined. It is then determined if at least one location of the one or more possible locations contains data to be stored in the location in memory. Data in one location of the at least one location is loaded, the data in the one location is from a store request of the one or more store requests and the store request is closest in the set of instructions to the load request.

公开(公告)号：US09471253B2

公开(公告)日：2016-10-18

申请号：US15015302

申请日：2016-02-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael T Benhase ,  Lokesh M. Gupta

IPC: G06F12/10 ,  G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0656 ,  G06F3/0608 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0673 ,  G06F3/0683 ,  G06F3/0688 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/0866 ,  G06F12/0897 ,  G06F2212/608 ,  G06F2212/7203 ,  G06F2212/7208

Abstract: For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, and at a time in which at least one data segment is to be migrated from one level to another level of the tiered levels of storage, a data migration mechanism is initiated by copying data resident in the lower-speed cache corresponding to the at least one data segment to be migrated to a target on the another level, reading remaining data, not previously copied from the lower-speed cache, from a source on the one level, and writing the remaining data to the target, and subsequent to the reading and the writing of the remaining data, destaging updates corresponding to the at least one data segment from either the higher and lower speed caches to the target.

Abstract translation: 对于由处理器设备在计算存储环境中的数据处理，计算存储环境至少包括高速和低速高速缓存以及层次级别的存储，并且在至少一个数据段将被迁移的时间 从分层存储的一个级别到另一级别，通过将驻留在低速缓存中的数据复制到待迁移的至少一个数据段上的数据复制到另一级别的目标来启动数据迁移机制，读取剩余的 先前未从低速缓存中复制的数据从一个级别的源写入剩余数据并将其余数据写入目标，然后在读取和写入其余数据之后，对与该至少一个 从高速缓存到低速缓存的数据段。

公开(公告)号：US09430372B2

公开(公告)日：2016-08-30

申请号：US13997940

申请日：2011-09-30

Applicant: Murugasamy K. Nachimuthu ,  Mohan Kumar

Inventor： Murugasamy K. Nachimuthu ,  Mohan Kumar

IPC: G06F12/00 ,  G06F12/02 ,  G06F9/44 ,  G06F13/14 ,  G06F12/08 ,  G11C13/00

CPC classification number: G06F12/0868 ,  G06F9/4401 ,  G06F9/4403 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0866 ,  G06F13/14 ,  G06F2212/1041 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/608 ,  G11C13/0004 ,  Y02D10/13

Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in the platform storage hierarchy. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM is coupled to the processor to be directly accessed by the processor without going through an I/O subsystem. The NVRAM stores a Basic Input and Output System (BIOS). During a Pre-Extensible Firmware Interface (PEI) phase of the boot process, the cache within the processor can be used in a write-back mode for execution of the BIOS.

Abstract translation: 在计算机系统中使用非易失性随机存取存储器（NVRAM）来在平台存储层级中执行多个角色。 NVRAM是字节可重写的，可由处理器字节擦除。 NVRAM被耦合到处理器以由处理器直接访问，而不经过I / O子系统。 NVRAM存储基本输入和输出系统（BIOS）。 在引导过程的预扩展固件接口（PEI）阶段期间，处理器内的缓存可以用于执行BIOS的回写模式。

公开(公告)号：US09424192B1

公开(公告)日：2016-08-23

申请号：US14677342

申请日：2015-04-02

Applicant: International Business Machines Corporation

Inventor： David M. Daly ,  Vijayalakshmi Srinivasan

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0815 ,  G06F3/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/084 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1048 ,  G06F2212/151 ,  G06F2212/251 ,  G06F2212/283 ,  G06F2212/608 ,  G06F2212/621

Abstract: A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.

Abstract translation: 在多处理器系统中提供用于存储器相干性的机制。 响应于来自多处理器系统的处理核心的存储器操作导致高速缓存未命中，该机制检查与处理核心相关联的专用区域表。 存储器操作尝试访问存储器区域。 响应于确定存储器区域对应于专用区域表中的条目，该机制执行远程存储器控制器的远程存储器控制器窥探器而不窥探多处理器系统。

公开(公告)号：US20160232067A1

公开(公告)日：2016-08-11

申请号：US14614841

申请日：2015-02-05

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Michael A. Blake ,  Michael Fee ,  Arthur J. O'Neill, JR.

IPC: G06F11/20 ,  G06F12/08

CPC classification number: G06F11/3037 ,  G06F11/073 ,  G06F11/0754 ,  G06F11/076 ,  G06F11/079 ,  G06F11/0793 ,  G06F11/08 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0897 ,  G06F12/128 ,  G06F2201/85 ,  G06F2201/885 ,  G06F2212/1032 ,  G06F2212/281 ,  G06F2212/283 ,  G06F2212/601 ,  G06F2212/608 ,  G06F2212/69

Abstract: In an approach for taking corrupt portions of cache offline during runtime, a notification of a section of a cache to be taken offline is received, wherein the section includes one or more sets in one or more indexes of the cache. An indication is associated with each set of the one or more sets in a first index of the one or more indexes, wherein the indication marks the respective set as unusable for future operations. Data is purged from the one or more sets in the first index of the cache. Each set of the one or more sets in the first index is marked as invalid.

Abstract translation: 在用于在运行时间内使缓存脱机的损坏部分的方法中，接收要脱机的高速缓存的一部分的通知，其中所述部分包括高速缓存的一个或多个索引中的一个或多个集合。 指示与一个或多个索引的第一索引中的一个或多个集合的每个集合相关联，其中该指示将相应集合标记为不可用于将来的操作。 从缓存的第一个索引中的一个或多个集合中清除数据。 第一个索引中的一个或多个集合的每个集合被标记为无效。

公开(公告)号：US20160232052A1

公开(公告)日：2016-08-11

申请号：US15097531

申请日：2016-04-13

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Michael A. Blake ,  Michael Fee ,  Arthur J. O'Neill, JR.

IPC: G06F11/07 ,  G06F12/08

CPC classification number: G06F11/3037 ,  G06F11/073 ,  G06F11/0754 ,  G06F11/076 ,  G06F11/079 ,  G06F11/0793 ,  G06F11/08 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0897 ,  G06F12/128 ,  G06F2201/85 ,  G06F2201/885 ,  G06F2212/1032 ,  G06F2212/281 ,  G06F2212/283 ,  G06F2212/601 ,  G06F2212/608 ,  G06F2212/69

Abstract: In an approach for taking corrupt portions of cache offline during runtime, a notification of a section of a cache to be taken offline is received, wherein the section includes one or more sets in one or more indexes of the cache. An indication is associated with each set of the one or more sets in a first index of the one or more indexes, wherein the indication marks the respective set as unusable for future operations. Data is purged from the one or more sets in the first index of the cache. Each set of the one or more sets in the first index is marked as invalid.