公开(公告)号：US07989280B2

公开(公告)日：2011-08-02

申请号：US12338839

申请日：2008-12-18

Applicant: Justin K. Brask ,  Suman Datta ,  Mark L. Doczy ,  James M. Blackwell ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Robert S. Chau

Inventor： Justin K. Brask ,  Suman Datta ,  Mark L. Doczy ,  James M. Blackwell ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L21/336

CPC classification number: H01L21/314 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28008 ,  H01L21/3141 ,  H01L21/31616 ,  H01L21/31645 ,  H01L29/2003 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7784

Abstract: A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.

Abstract translation: 描述了III-V族半导体器件及其制造方法。 高k电介质通过硫族化物区域连接到约束区域。

公开(公告)号：US20110147798A1

公开(公告)日：2011-06-23

申请号：US12646711

申请日：2009-12-23

Applicant: Marko Radosavljevic ,  Prashant Majhi ,  Jack T. Kavalieros ,  Niti Goel ,  Wilman Tsai ,  Niloy Mukherjee ,  Yong Ju Lee ,  Gilbert Dewey ,  Willy Rachmady

Inventor： Marko Radosavljevic ,  Prashant Majhi ,  Jack T. Kavalieros ,  Niti Goel ,  Wilman Tsai ,  Niloy Mukherjee ,  Yong Ju Lee ,  Gilbert Dewey ,  Willy Rachmady

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/7786 ,  H01L21/2256 ,  H01L29/20 ,  H01L29/42316 ,  H01L29/47 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

Abstract: Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.

Abstract translation: 描述了III-V半导体器件的电导率改进。 第一改进包括与通道层不共同平面的阻挡层。 第二个改进包括金属/ Si，Ge或硅锗/ III-V堆叠的退火，以在Si和/或锗掺杂的III-V层上形成金属硅，金属锗或金属硅锗层。 然后，去除金属层并在金属硅，金属锗或金属硅锗层上形成源/漏电极。 第三个改进包括在III-V沟道层上形成IV族和/或VI族元素的层，以及退火以使IV族和/或VI族物质掺杂III-V通道层。 第四个改进包括在III-V器件的接近区域上形成的钝化层和/或偶极层。

公开(公告)号：US07902014B2

公开(公告)日：2011-03-08

申请号：US11649545

申请日：2007-01-03

Applicant: Brian S. Doyle ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta ,  Justin K. Brask ,  Robert S. Chau

Inventor： Brian S. Doyle ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta ,  Justin K. Brask ,  Robert S. Chau

IPC: H01L21/8234

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.

Abstract translation: 这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。 本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。

公开(公告)号：US20110008937A1

公开(公告)日：2011-01-13

申请号：US12885071

申请日：2010-09-17

Applicant: Been-Yih Jin ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Robert S. Chau

Inventor： Been-Yih Jin ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L21/84

CPC classification number: H01L21/02381 ,  B82Y10/00 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/31658 ,  H01L21/76283 ,  H01L21/823807 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42324 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region.

Abstract translation: 一种提供晶体管或存储单元结构的方法。 该方法包括：在衬底上提供包括下Si衬底和绝缘层的衬底; 提供在所述绝缘层上方延伸的第一突起，所述第一突起包括Si材料和Si1-xGex材料; 以及将所述第一突起暴露于优先氧化以产生包括包含Ge / Si1-yGey的中心区域和包含SiO 2并包围所述中心区域的覆盖区域的第二突起。

公开(公告)号：US20100327261A1

公开(公告)日：2010-12-30

申请号：US12876922

申请日：2010-09-07

Applicant: Mantu K. Hudait ,  Suman Datta ,  Jack T. Kavalieros ,  Peter G. Tolchinsky

Inventor： Mantu K. Hudait ,  Suman Datta ,  Jack T. Kavalieros ,  Peter G. Tolchinsky

IPC: H01L29/775 ,  H01L29/20

CPC classification number: H01L29/7782 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/02573 ,  H01L21/0262 ,  H01L29/267 ,  H01L29/66431

Abstract: The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Abstract translation: 本公开提供了一种在硅（“Si”）衬底上实现高空穴迁移率p沟道锗（“Ge”）晶体管结构的装置和方法。 一个示例性装置可以包括包括GaAs成核层，第一GaAs缓冲层和第二GaAs缓冲层的缓冲层。 该示例性装置还可以包括第二GaAs缓冲层上的底部阻挡层，并具有大于1.1eV的带隙，底部势垒上的Ge活性通道层，并且相对于底部势垒的价带偏移大于0.3 eV和Ge活性通道层上的AlAs顶部势垒，其中AlAs顶部势垒具有大于1.1eV的带隙。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US20100289062A1

公开(公告)日：2010-11-18

申请号：US12454354

申请日：2009-05-15

Applicant: Ravi Pillarisetty ,  Mantu Uudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

Inventor： Ravi Pillarisetty ,  Mantu Uudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

IPC: H01L29/20

CPC classification number: H01L29/66522 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/205 ,  H01L29/66477

Abstract: A surface channel transistor is provided in a semiconductive device. The surface channel transistor is either a PMOS or an NMOS device. Epitaxial layers are disposed above the surface channel transistor to cause an increased bandgap phenomenon nearer the surface of the device. A process of forming the surface channel transistor includes grading the epitaxial layers.

Abstract translation: 表面沟道晶体管设置在半导体器件中。 表面沟道晶体管是PMOS或NMOS器件。 外延层设置在表面沟道晶体管的上方，导致更接近器件表面的带隙现象增加。 形成表面沟道晶体管的工艺包括对外延层进行分级。

公开(公告)号：US07825400B2

公开(公告)日：2010-11-02

申请号：US11450745

申请日：2006-06-09

Applicant: Suman Datta ,  Jack T. Kavalieros ,  Been-Yih Jin

Inventor： Suman Datta ,  Jack T. Kavalieros ,  Been-Yih Jin

IPC: H01L29/06 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336

CPC classification number: H01L29/1033 ,  H01L29/0673 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/66431 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66787 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785

Abstract: A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.

Abstract translation: 描述形成应变诱导半导体区域的方法。 在一个实施方案中，形成横向邻近晶体衬底的应变诱导半导体区域导致赋予晶体衬底的单轴应变，从而提供应变的晶体衬底。 在另一个实施方案中，具有一种或多种电荷 - 中性晶格形成原子的晶格的半导体区域向晶体衬底赋予应变，其中半导体区域的晶格常数与晶体衬底的晶格常数不同，以及 其中所述半导体区域的电荷 - 中性晶格形成原子的所有种类都包含在所述晶体衬底中。

公开(公告)号：US20100163945A1

公开(公告)日：2010-07-01

申请号：US12319101

申请日：2008-12-30

Applicant: Jack T. Kavalieros ,  Niloy Mukherjee ,  Gilbert Dewey ,  Dinesh Somasekhar ,  Brian S. Doyle

Inventor： Jack T. Kavalieros ,  Niloy Mukherjee ,  Gilbert Dewey ,  Dinesh Somasekhar ,  Brian S. Doyle

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L29/66181 ,  H01L27/10832 ,  H01L27/10861 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/10876 ,  H01L28/90 ,  H01L29/66666 ,  H01L29/7827

Abstract: An embedded memory cell includes a semiconducting substrate (110), a transistor (120) having a source/drain region (121) at least partially embedded in the semiconducting substrate, and a capacitor (130) at least partially embedded in the semiconducting substrate. The capacitor includes a first electrode (131) and a second electrode (132) that are electrically isolated from each other by a first electrically insulating material (133). The first electrode is electrically connected to the semiconducting substrate and the second electrode is electrically connected to the source/drain region of the transistor.

Abstract translation: 嵌入式存储单元包括半导体衬底（110），具有至少部分地嵌入在半导体衬底中的源极/漏极区域（121）的晶体管（120）以及至少部分地嵌入在半导体衬底中的电容器（130）。 电容器包括通过第一电绝缘材料（133）彼此电绝缘的第一电极（131）和第二电极（132）。 第一电极电连接到半导体衬底，第二电极电连接到晶体管的源极/漏极区域。

公开(公告)号：US20100163926A1

公开(公告)日：2010-07-01

申请号：US12345489

申请日：2008-12-29

Applicant: Mantu K. Hudait ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

Inventor： Mantu K. Hudait ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

IPC: H01L29/267 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/66795

Abstract: Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or more buffer films, a multi-gate fin coupled to the first barrier film, the multi-gate fin comprising a source region, a drain region, and a channel region of a multi-gate device wherein the channel region is disposed between the source region and the drain region, a spacer film coupled to the multi-gate fin, and a doped film coupled to the spacer film.

Abstract translation: 通常描述调制掺杂多栅极器件。 在一个示例中，设备包括具有表面的半导体衬底，耦合到半导体衬底的表面的一个或多个缓冲膜，耦合到该一个或多个缓冲膜的第一阻挡膜，耦合到第一 所述多栅极鳍片包括源极区域，漏极区域和多栅极器件的沟道区域，其中所述沟道区域设置在所述源极区域和所述漏极区域之间，间隔膜耦合到所述多栅极器件， 栅极鳍片以及耦合到间隔膜的掺杂膜。

公开(公告)号：US07629643B2

公开(公告)日：2009-12-08

申请号：US11948414

申请日：2007-11-30

Applicant: Ravi Pillarisetty ,  Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle

Inventor： Ravi Pillarisetty ,  Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle

IPC: H01L27/108

CPC classification number: H01L27/1104 ,  H01L27/0207 ,  H01L27/11 ,  H01L29/785

Abstract: Independent n-tips for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) devices coupled with the semiconductor fin, the one or more PD devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PD devices, and one or more multi-gate pass gate (PG) devices coupled with the semiconductor fin, the one or more PG devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PG devices, wherein the n-tip dopant concentration for the PG device is lower than the n-tip dopant concentration for the PD device.

Abstract translation: 通常描述多栅极晶体管的独立n尖端。 在一个示例中，设备包括半导体鳍片，与半导体鳍片耦合的一个或多个多栅极下拉（PD）器件，所述一个或多个PD器件在与半导体鳍片材料相邻的半导体鳍片材料中具有n尖端掺杂剂浓度 一个或多个PD器件，以及与半导体鳍片耦合的一个或多个多栅极通过栅极（PG）器件，所述一个或多个PG器件在与所述一个或多个PG相邻的半导体鳍片材料中具有n尖端掺杂剂浓度 器件，其中PG器件的n尖掺杂剂浓度低于PD器件的n尖掺杂剂浓度。