公开(公告)号：US20140104948A1

公开(公告)日：2014-04-17

申请号：US13836028

申请日：2013-03-15

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Hyoung Seub RHIE

IPC: G11C16/08

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C11/4085 ,  G11C16/0483

Abstract: A non-volatile memory device having a memory array organized into a plurality of memory blocks, having either planar memory cells or stacks of cells. Row decoding circuitry of the memory device is configured to select a group of the plurality of memory blocks in response to a first row address, and to select a memory block of the group for receiving row signals in response to a second row address. Row decoding circuitry associated with each group of memory blocks can have a row pitch spacing that is greater than a row pitch spacing of a single memory block and less than or equal to a total row pitch spacing corresponding to the group of memory blocks.

Abstract translation: 具有组织成多个存储器块的存储器阵列的非易失性存储器件，具有平面存储单元或单元堆叠。 存储器件的行解码电路被配置为响应于第一行地址来选择多个存储器块的组，并且响应于第二行地址选择用于接收行信号的组的存储器块。 与每组存储器块相关联的行解码电路可以具有大于单个存储器块的行间距间隔的行间距间隔，并且小于或等于对应于该组存储器块的总行间距间隔。

公开(公告)号：US20140092743A1

公开(公告)日：2014-04-03

申请号：US14097614

申请日：2013-12-05

Applicant: MOSAID Technologies Incorporated

Inventor： David A. BROWN

IPC: H04L12/861 ,  H04L12/911

CPC classification number: H04L47/30 ,  H04L47/70 ,  H04L49/103 ,  H04L49/201 ,  H04L49/252 ,  H04L49/9047

Abstract: A switch includes a reserved pool of buffers in a shared memory. The reserved pool of buffers is reserved for exclusive use by an egress port. The switch includes pool select logic which selects a free buffer from the reserved pool for storing data received from an ingress port to be forwarded to the egress port. The shared memory also includes a shared pool of buffers. The shared pool of buffers is shared by a plurality of egress ports. The pool select logic selects a free buffer in the shared pool upon detecting no free buffer in the reserved pool. The shared memory may also include a multicast pool of buffers. The multicast pool of buffers is shared by a plurality of egress ports. The pool select logic selects a free buffer in the multicast pool upon detecting an IP Multicast data packet received from an ingress port.

Abstract translation: 交换机在共享存储器中包括一个保留的缓冲区池。 保留的缓冲池被保留供出口端口独占使用。 该交换机包括池选择逻辑，其从保留池中选择一个空闲缓冲区，用于存储从入口端口接收的数据以转发到出口端口。 共享内存还包括一个共享的缓冲池。 共享缓冲区池由多个出口端口共享。 池选择逻辑在检测到预留池中没有可用缓冲区时，会选择共享池中的空闲缓冲区。 共享存储器还可以包括缓冲器的多播池。 缓冲区的组播池由多个出口端口共享。 池选择逻辑在检测到从入口端口接收到的IP组播数据包时，选择多播池中的空闲缓冲区。

公开(公告)号：US08638638B2

公开(公告)日：2014-01-28

申请号：US13732791

申请日：2013-01-02

Applicant: MOSAID Technologies Incorporated

Inventor： Richard C. Foss ,  Peter B. Gillingham ,  Graham Allan

IPC: G11C8/00

CPC classification number: G11C11/4076 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03L7/0814

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

Abstract translation: 用于同步存储器的时钟施加电路包括用于接收时钟输入信号的时钟输入，连接到用于接收驱动时钟信号的同步存储器的装置和用于接收用于传送时钟驱动的时钟输入信号的抽头延迟线 与时钟输入信号同步但延迟到同步存储器，延迟是时钟输入信号的时钟周期的一小部分。

公开(公告)号：US08619473B2

公开(公告)日：2013-12-31

申请号：US13649403

申请日：2012-10-11

Applicant: Mosaid Technologies Incorporated

Inventor： Jin-Ki Kim ,  Peter Gillingham

IPC: G11C16/00

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/143 ,  G11C5/145 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

公开(公告)号：US20130343142A1

公开(公告)日：2013-12-26

申请号：US13973574

申请日：2013-08-22

Applicant: Mosaid Technologies Incorporated

Inventor： Hong Beom PYEON

IPC: G11C5/14

CPC classification number: G11C11/4074 ,  G11C5/145 ,  G11C11/406 ,  G11C11/4076 ,  G11C2211/4061 ,  G11C2211/4067 ,  G11C2211/4068 ,  H02M3/073 ,  H02M2003/077

Abstract: A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode.

公开(公告)号：US20130336055A1

公开(公告)日：2013-12-19

申请号：US13973600

申请日：2013-08-22

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Hong Beom PYEON

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C8/08 ,  G11C8/14 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C2013/0071

Abstract: A method for improving sub-word line response comprises generating a variable substrate bias determined by at least one user parameter. The variable substrate bias is applied to a sub-word line driver in a selected sub-block of a memory. A voltage disturbance on a sub-word line in communication with the sub-word line driver is minimized by modifying a variable substrate bias of the sub-word line driver to change a transconductance of the sub-word line driver thereby.

公开(公告)号：US20130329482A1

公开(公告)日：2013-12-12

申请号：US13966891

申请日：2013-08-14

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Peter B. GILLINGHAM ,  Bruce MILLAR

IPC: G11C5/06

CPC classification number: G11C5/06 ,  G06F1/12 ,  G06F13/1689 ,  G06F13/4234 ,  G06F13/4243 ,  G11C8/18 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory module that includes a buffer and a plurality of synchronous memory devices. The memory module also includes bidirectional bus lines, and each of the synchronous memory devices has bidirectional data terminals. The buffer is configured to regenerate signals received on the bus lines for receipt by the synchronous memory devices, and to regenerate signals received from any one of the synchronous memory devices for receipt by the bus lines. The memory module may further include command lines and a clock line for providing commands and a clock signal to the synchronous memory devices via a command buffer. The combined data bus width of the memory module may be greater than the data bus width of any single one of synchronous memory device, and the total address space provided by the memory module may be larger than the data space for any single synchronous memory device.

公开(公告)号：US20130309810A1

公开(公告)日：2013-11-21

申请号：US13951132

申请日：2013-07-25

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Peter GILLINGHAM

IPC: H01L21/82

CPC classification number: H01L21/82 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2224/48145 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed.

Abstract translation: 半导体器件具有安装在基板上的多个堆叠的半导体管芯。 每个模具具有相似的尺寸。 每个管芯具有沿着管芯的接合边缘布置的第一多个接合焊盘。 将第一组骰子安装到衬底上，其中接合边缘沿第一方向定向。 将第二组骰子安装到基板上，其中接合边缘沿与第一方向相反的第二方向定向。 每个模具相对于剩余的骰子在第二方向上通过相应的横向偏移距离而在第二方向上侧向偏移，使得每个模具的焊盘不会在垂直于衬底的方向上设置在衬底和剩余骰子的任何部分之间。 多个接合线将接合焊盘连接到衬底。 还公开了半导体器件的制造方法。

公开(公告)号：US20130271910A1

公开(公告)日：2013-10-17

申请号：US13917728

申请日：2013-06-14

Applicant: MOSAID Technologies Incorporated

Inventor： Jin-Ki Kim

IPC: G06F1/16

CPC classification number: G06F1/16 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0679 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/14 ,  H05K3/284 ,  H05K2201/10159 ,  H05K2203/049 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A solid state drive is disclosed. The solid state drive includes a circuit board having opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the circuit board of the solid state drive, and the plurality of semiconductor chips of the solid state drive include at least one memory chip that is at least substantially encapsulated in a resin. An in-line memory module-type form factor circuit board is also disclosed. The in-line memory module-type form factor circuit board has opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the in-line memory module-type form factor circuit board, and these semiconductor chips include at least one memory chip that is at least substantially encapsulated in a resin.

Abstract translation: 公开了一种固态驱动器。 固态驱动器包括具有相对的第一和第二表面的电路板。 多个半导体芯片附接到固态驱动器的电路板的第一表面，并且固态驱动器的多个半导体芯片包括至少基本上封装在树脂中的至少一个存储器芯片。 还公开了一种在线存储器模块型形状电路板。 在线存储器模块型外形电路板具有相对的第一和第二表面。 多个半导体芯片附接到直列式存储模块型形状电路板的第一表面，并且这些半导体芯片包括至少基本上封装在树脂中的至少一个存储芯片。

公开(公告)号：US20130237182A1

公开(公告)日：2013-09-12

申请号：US13867158

申请日：2013-04-22

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Dan SCHLAGER ,  William B. BARINGER

IPC: H04W4/22

CPC classification number: H04W4/90 ,  A61N1/08 ,  B63C9/0005 ,  G08B13/1427 ,  G08B19/00 ,  G08B21/0211 ,  G08B21/0227 ,  G08B21/023 ,  G08B21/0255 ,  G08B21/028 ,  G08B21/0283 ,  G08B21/0286 ,  G08B21/0288 ,  G08B21/0294 ,  G08B21/088 ,  G08B25/016 ,  G08B25/10 ,  G08B26/007

Abstract: A personal alarm system includes a monitoring base station and one or more remote sensing units in two-way radio communication. An electronic handshake between the base station and each remote unit is used to assure system reliability. The remote units transmit at selectable power levels. In the absence of an emergency, a remote unit transmits at a power-conserving low power level. Received field strength is measured to determine whether a remote unit has moved beyond a predetermined distance from the base station. If the distance is exceeded, the remote unit transmits at a higher power level. The remote unit includes sensors for common hazards including water emersion, smoke, excessive heat, excessive carbon monoxide concentration, and electrical shock. The base station periodically polls the remote units and displays the status of the environmental sensors. The system is useful in child monitoring, for use with invalids and with employees involved in activities which expose them to environmental risk. Alternative embodiments include a panic button on the remote unit for summoning help, and an audible beacon on the remote unit which can be activated from the base station and useful for locating strayed children. In another embodiment, the remote unit includes a Global Positioning System receiver providing location information for display by the base station.

Abstract translation: 个人报警系统包括监视基站和双向无线电通信中的一个或多个遥感单元。 使用基站和每个远程单元之间的电子握手来确保系统的可靠性。 远程单元以可选择的功率级发送。 在没有紧急情况的情况下，远程单元以节能低功率发射。 测量接收的场强以确定远程单元是否已经移动超出距离基站的预定距离。 如果超出该距离，则远程单元以较高的功率级发射。 远程单元包括用于常见危害的传感器，包括水浸，烟雾，过热，过量的一氧化碳浓度和电击。 基站周期性地轮询远程单元并显示环境传感器的状态。 该系统对儿童监测有用，用于残疾人和参与活动的员工，使他们面临环境风险。 替代实施例包括远程单元上的紧急按钮，用于召唤帮助，以及远程单元上的可听信标，其可以从基站激活并且有助于定位迷路儿童。 在另一个实施例中，远程单元包括提供用于由基站显示的位置信息的全球定位系统接收器。