公开(公告)号：US20120124830A1

公开(公告)日：2012-05-24

申请号：US13362958

申请日：2012-01-31

Applicant: David C. H. Cheng ,  Shao-Chien Lee ,  Tzyy-Jang Tseng

Inventor： David C. H. Cheng ,  Shao-Chien Lee ,  Tzyy-Jang Tseng

IPC: H05K3/10

CPC classification number: H05K3/4007 ,  H05K3/06 ,  H05K3/062 ,  H05K3/107 ,  H05K3/3452 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/099 ,  H05K2203/0384 ,  H05K2203/0542 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A process for fabricating a circuit board is provided. In the process, first, a circuit substrate including an insulation layer and at least a pad contacting the insulation layer is provided. Next, a barrier material layer is formed on the circuit substrate. The barrier material layer completely covers the insulation layer and the pad. Then, at least one conductive bump is formed on the barrier material layer. The conductive bump is opposite to the pad, and the material of the barrier material layer is different from the material of the conductive bump. Next, a portion of the barrier material layer is removed by using the conductive bump as a mask, so as to expose the surface of the insulation layer and to form a barrier connected between the conductive bump and the pad.

Abstract translation: 提供一种制造电路板的工艺。 在该过程中，首先，提供包括绝缘层和至少与绝缘层接触的焊盘的电路基板。 接下来，在电路基板上形成阻挡材料层。 阻挡材料层完全覆盖绝缘层和垫。 然后，在阻挡材料层上形成至少一个导电凸块。 导电凸块与焊盘相对，并且阻挡材料层的材料与导电凸块的材料不同。 接下来，通过使用导电凸块作为掩模来去除阻挡材料层的一部分，以暴露绝缘层的表面并形成连接在导电凸块和焊盘之间的阻挡层。

公开(公告)号：US20120031652A1

公开(公告)日：2012-02-09

申请号：US13050009

申请日：2011-03-17

Applicant: TZYY-JANG TSENG ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

Inventor： TZYY-JANG TSENG ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

IPC: H05K1/00 ,  C25D5/02 ,  H05K3/00 ,  H05K3/10 ,  H05K3/12

CPC classification number: H05K3/12 ,  C23C18/1605 ,  C23C18/165 ,  C25D5/022 ,  H05K1/0203 ,  H05K1/056 ,  H05K3/02 ,  H05K3/181 ,  H05K3/188 ,  H05K3/3436 ,  H05K2201/0187 ,  Y10T29/302 ,  Y10T29/49155 ,  Y10T156/10

Abstract: A circuit board includes a metal pattern layer, a thermally conductive plate, an electrically insulating layer, and at least one electrically insulating material. The thermally conductive plate has a plane. The electrically insulating layer is disposed between the metal pattern layer and the plane and partially covers the plane. The electrically insulating material covers the plane where is not covered by the electrically insulating layer and touches the thermally conductive plate. The electrically insulating layer exposes the electrically insulating material, and a thermal conductivity of the electrically insulating material is larger than a thermal conductivity of the electrically insulating layer.

Abstract translation: 电路板包括金属图案层，导热板，电绝缘层和至少一个电绝缘材料。 导热板具有平面。 电绝缘层设置在金属图案层和平面之间并且部分覆盖平面。 电绝缘材料覆盖未被电绝缘层覆盖并接触导热板的平面。 电绝缘层暴露电绝缘材料，并且电绝缘材料的热导率大于电绝缘层的热导率。

公开(公告)号：US07906200B2

公开(公告)日：2011-03-15

申请号：US12424057

申请日：2009-04-15

Applicant: Tzyy-Jang Tseng ,  Chih-Peng Fan

Inventor： Tzyy-Jang Tseng ,  Chih-Peng Fan

IPC: B32B9/00

CPC classification number: H05K3/045 ,  H05K1/036 ,  H05K1/0366 ,  H05K3/107 ,  H05K3/185 ,  H05K2201/0236 ,  H05K2201/029 ,  H05K2203/0723 ,  H05K2203/107 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: A composite circuit substrate structure includes a first dielectric layer, a second dielectric layer, a glass fiber structure, and a patterned circuit. The first dielectric layer has a first surface and a second surface opposite to each other. The second dielectric layer is disposed on the first dielectric layer and entirely connected to the first surface. The glass fiber structure is distributed in the second dielectric layer. The patterned circuit is embedded in the first dielectric layer from the second surface, and the patterned circuit is not contacted with the glass fiber structure.

Abstract translation: 复合电路基板结构包括第一电介质层，第二电介质层，玻璃纤维结构和图案化电路。 第一介电层具有彼此相对的第一表面和第二表面。 第二电介质层设置在第一电介质层上并且完全连接到第一表面。 玻璃纤维结构分布在第二电介质层中。 图案化电路从第二表面嵌入第一电介质层中，并且图案化电路不与玻璃纤维结构接触。

公开(公告)号：US20090166059A1

公开(公告)日：2009-07-02

申请号：US12048909

申请日：2008-03-14

Applicant: Tsung-Yuan Chen ,  Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  David C. H. Cheng

Inventor： Tsung-Yuan Chen ,  Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  David C. H. Cheng

IPC: H05K1/00 ,  H05K3/10

CPC classification number: H05K1/0219 ,  H05K3/20 ,  H05K2201/0376 ,  H05K2201/09236 ,  H05K2201/09736 ,  Y10T29/49155

Abstract: A circuit board and process thereof are provided. The circuit board includes a dielectric layer, a main circuit, and two shielding circuits. The dielectric layer has an active surface. The main circuit is embedded in the dielectric layer and the shielding circuits are disposed at the dielectric layer. The shielding circuits are respectively located at two sides of the main circuit. The thickness of the shielding circuits is larger than the thickness of the main circuit.

Abstract translation: 提供电路板及其工艺。 电路板包括电介质层，主电路和两个屏蔽电路。 电介质层具有活性表面。 主电路嵌入电介质层，屏蔽电路设置在电介质层。 屏蔽电路分别位于主电路的两侧。 屏蔽电路的厚度大于主电路的厚度。

公开(公告)号：US20070153488A1

公开(公告)日：2007-07-05

申请号：US11554882

申请日：2006-10-31

Applicant: Ming-Huan Yang ,  Chung-Wei Wang ,  Chia-Chi Wu ,  Chao-Kai Cheng ,  Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Cheng-Po Yu ,  Cheng-Hung Yu

Inventor： Ming-Huan Yang ,  Chung-Wei Wang ,  Chia-Chi Wu ,  Chao-Kai Cheng ,  Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Cheng-Po Yu ,  Cheng-Hung Yu

IPC: H05K7/00 ,  H05K3/10

CPC classification number: H05K3/182 ,  H05K3/389 ,  H05K3/421 ,  H05K3/422 ,  H05K3/426 ,  H05K3/4661 ,  H05K2203/013 ,  H05K2203/0565 ,  H05K2203/0709 ,  Y10T29/49155

Abstract: A method for fabricating a double-sided or multi-layer printed circuit board (PCB) by ink-jet printing that includes providing a substrate, forming a first self-assembly membrane (SAM) on at least one side of the substrate, forming a non-adhesive membrane on the first SAM, forming at least one microhole in the substrate, forming a second SAM on a surface of the microhole, providing catalyst particles on the at least one side of the substrate and on the surface of the microhole, and forming a catalyst circuit pattern on the substrate.

Abstract translation: 一种通过喷墨印刷制造双面或多层印刷电路板（PCB）的方法，其包括提供基板，在所述基板的至少一侧上形成第一自组装膜（SAM），形成 在所述第一SAM上形成非粘性膜，在所述基底中形成至少一个微孔，在所述微孔的表面上形成第二SAM，在所述基底的至少一侧和所述微孔的表面上提供催化剂颗粒，以及 在基板上形成催化剂电路图案。

公开(公告)号：US20070151845A1

公开(公告)日：2007-07-05

申请号：US11430948

申请日：2006-05-10

Applicant: Chieh-Kai Chang ,  Chao-Kai Cheng ,  Ming-Huan Yang ,  Chung-Wei Wang ,  Fu-Kang Cheng ,  Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Chih-Ming Chang ,  Cheng-Po Yu

Inventor： Chieh-Kai Chang ,  Chao-Kai Cheng ,  Ming-Huan Yang ,  Chung-Wei Wang ,  Fu-Kang Cheng ,  Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Chih-Ming Chang ,  Cheng-Po Yu

IPC: C25C7/00

CPC classification number: C25D17/00 ,  C25D5/003 ,  C25D5/08 ,  C25D17/004 ,  C25D17/02 ,  C25D21/12 ,  H05K3/423 ,  H05K2203/074 ,  H05K2203/1518

Abstract: An apparatus for metal plating on a substrate with through-holes includes a chamber that the substrate is disposed inside the chamber to be divided into two sections. A pressure generator and a pressure controller are connected to this and correspond to two sides of the substrate respectively. The pressure generator is used for pumping a electrolyte flowed parallel to the surface of the substrate into the chamber. The pressure controller is used for channeling the electrolyte off the chamber and controlling the pressure differences between the two sides of the substrate. So that the electrolyte flowed parallel to the surface of the substrate is pumped by the pressure generator and it passes several through-holes to control the thickness of metal plating on the.substrate and inner walls of the through-holes.

Abstract translation: 用于在具有通孔的基板上进行金属电镀的设备包括：室，其设置在室内，以分成两部分。 压力发生器和压力控制器分别连接到基板的两侧。 压力发生器用于将平行于衬底的表面流动的电解质泵入室中。 压力控制器用于将电解质引出室，并控制衬底两侧之间的压力差。 使得平行于基板表面流动的电解质被压力发生器泵送，并且通过几个通孔以控制通孔的内壁和内壁上的金属镀层的厚度。

公开(公告)号：US6057601A

公开(公告)日：2000-05-02

申请号：US200691

申请日：1998-11-27

Applicant: John H. Lau ,  Tzyy Jang Tseng ,  Chen-Hua Cheng

Inventor： John H. Lau ,  Tzyy Jang Tseng ,  Chen-Hua Cheng

IPC: H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H01L23/48

CPC classification number: H01L23/36 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15747 ,  H01L2924/181

Abstract: The present invention discloses a new semiconductor ball grid array package for integrated circuits which have input and output counts higher than 250. The speed and performance characteristics of the semiconductor device contained in the package assembly are optimized while the packaging structure is simplified by utilizing only one dielectric layer and regular printed circuit board fabrication process. The complexities and higher cost for production of a multiple layer substrate for high-density interconnection configuration are thus resolved. The improved package assembly is achieved by implementing a segmented ring on one side of a substrate and a split plane on the other side thus forming a single layer substrate structure. The edges of the substrate are coated with metal layer to provide interlayer connections. The package assembly applies a cavity down configuration with an integrated heat spreader attached. The IC wire bonds within the cavity are sealed with an organic encapsulant. In addition to the benefits of high performance low cost, the improved circuit structure and package layout provide flexibility allowing higher degree of freedom for selecting the location and number of input and output signal lines and connections to the ground and power planes from the semiconductor device.

Abstract translation: 本发明公开了一种用于集成电路的新型半导体球栅阵列封装，其输入和输出计数高于250.包装组件中所包含的半导体器件的速度和性能特性被优化，同时通过仅使用一个 电介质层和常规印刷电路板制造工艺。 因此解决了用于生产用于高密度互连配置的多层基板的复杂性和更高的成本。 改进的封装组件通过在衬底的一侧上实现分段环并在另一侧上实现分裂平面来实现，从而形成单层衬底结构。 衬底的边缘涂有金属层以提供层间连接。 封装组件采用附有散热器的空腔向下配置。 腔内的IC引线键合用有机密封剂密封。 除了高性能低成本的优点之外，改进的电路结构和封装布局提供了灵活性，允许更高的自由度来选择输入和输出信号线的位置和数量以及从半导体器件到地面和电源平面的连接。