公开(公告)号：US5451532A

公开(公告)日：1995-09-19

申请号：US273530

申请日：1994-07-11

Applicant: Rashid Bashir ,  Francois Hebert

Inventor： Rashid Bashir ,  Francois Hebert

IPC: H01L21/8249 ,  H01L21/8222

CPC classification number: H01L21/8249 ,  Y10S148/01 ,  Y10S257/90

Abstract: A bipolar transistor in accordance with the invention includes a polysilicon base contact (607A) which is self-aligned with a polysilicon emitter (303). The polysilicon emitter is formed from a first polysilicon layer overlying an intrinsic base region (502) in a substrate (201). An extrinsic base (504) in the substrate is in contact with the intrinsic base and is self-aligned with a spacer (406) adjacent to the emitter. The polysilicon base contact is formed from a second polysilicon layer (407) in contact with the extrinsic base and overlying the emitter. A second sidewall spacer (508) is formed on the second polysilicon layer on step caused by the emitter. A protective layer (509, 510) formed on portions of the second polysilicon layer protects the base contact when the second spacer and the underlying portion of the second polysilicon layer are removed. The separation between the polysilicon base contact and the polysilicon emitter is controlled by the thickness the second polysilicon layer and the thickness of the spacers so that the base contact is self-aligned with a fixed separation from the emitter. Layer and spacer thicknesses define separation between the emitter and the base contact and permit sub-micron active regions in the substrate.

Abstract translation: 根据本发明的双极晶体管包括与多晶硅发射器（303）自对准的多晶硅基极接触（607A）。 多晶硅发射体由覆盖衬底（201）中的本征基极区（502）的第一多晶硅层形成。 衬底中的外在基极（504）与本征基极接触并且与邻近发射极的间隔物（406）自对准。 多晶硅基极接触由与外部基极接触并覆盖发射极的第二多晶硅层（407）形成。 第二侧壁间隔物（508）由发射极引起的步骤形成在第二多晶硅层上。 形成在第二多晶硅层的部分上的保护层（509,510）在去除第二间隔物和第二多晶硅层的下面部分时保护基极接触。 多晶硅基底触点和多晶硅发射极之间的间隔由第二多晶硅层的厚度和间隔物的厚度来控制，使得基极接触件与发射极的固定分离自对准。 层和间隔物厚度限定了发射极和基极接触之间的间隔，并允许衬底中的亚微米有源区。

公开(公告)号：US5439833A

公开(公告)日：1995-08-08

申请号：US213630

申请日：1994-03-15

Applicant: Francois Hebert ,  Datong Chen ,  Rashid Bashir

Inventor： Francois Hebert ,  Datong Chen ,  Rashid Bashir

IPC: H01L21/8249 ,  H01L27/06 ,  H01L21/265

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  Y10S148/009

Abstract: A truly complementary bipolar transistor structure and a combined bipolar and CMOS transistor structure are disclosed, each including a silicide layer formed upon a substrate that acts as an extrinsic base and gate. Optionally, a layer of polysilicon can be formed between the silicide layer and the substrate. An oxide layer (LTO) is formed or deposited over the silicide layer by chemical vapor deposition (CVD). Selected regions are defined and etched using a photoresist layer. Subsequent steps of implanting, etching and metalization are performed to produce transistors with reduced gate and extrinsic base resistances. Polysilicon may be used, instead of metal, as a contact in one embodiment of the invention.

Abstract translation: 公开了一种真正互补的双极晶体管结构和组合的双极和CMOS晶体管结构，每个晶体管结构包括形成在用作外部基极和栅极的衬底上的硅化物层。 可选地，可以在硅化物层和衬底之间形成多晶硅层。 通过化学气相沉积（CVD）在硅化物层上形成或沉积氧化物层（LTO）。 使用光致抗蚀剂层限定和蚀刻所选择的区域。 进行植入，蚀刻和金属化的后续步骤以产生具有减小的栅极和非本征基极电阻的晶体管。 在本发明的一个实施方案中，可以使用多晶硅代替金属作为接触。

公开(公告)号：US08815641B2

公开(公告)日：2014-08-26

申请号：US12719988

申请日：2010-03-09

Applicant: Rick C. Jerome ,  Francois Hebert ,  Craig McLachlan ,  Kevin Hoopingarner

Inventor： Rick C. Jerome ,  Francois Hebert ,  Craig McLachlan ,  Kevin Hoopingarner

IPC: H01L29/06 ,  H01L21/20

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/02444 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02521 ,  H01L21/76254 ,  H01L23/3732 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for a semiconductor device including a thin nitride layer formed between a diamond SOI layer and device silicon layer to block diffusion of ions and improve lifetime of the device silicon.

Abstract translation: 一种半导体器件的方法和结构，包括在金刚石SOI层和器件硅层之间形成的薄氮化物层，以阻止离子的扩散并提高器件硅的寿命。

公开(公告)号：US08637360B2

公开(公告)日：2014-01-28

申请号：US12950202

申请日：2010-11-19

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L21/338

CPC classification number: H01L27/0255 ,  H01L21/8258 ,  H01L27/0629 ,  H01L27/0688 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/8611 ,  H01L29/872

Abstract: Exemplary embodiments provide structures and methods for power devices with integrated clamp structures. The integration of clamp structures can protect the power device, e.g., from electrical overstress (EOS). In one embodiment, active devices can be formed over a substrate, while a clamp structure can be integrated outside the active regions of the power device, for example, under the active regions and/or inside the substrate. Integrating clamp structure outside active regions of power devices can maximize the active area for a given die size and improve robustness of the clamped device since the current will spread in the substrate by this integration.

Abstract translation: 示例性实施例提供了具有集成钳位结构的功率器件的结构和方法。 夹紧结构的集成可以保护功率器件，例如不受电力过应力（EOS）的影响。 在一个实施例中，有源器件可以形成在衬底上，而钳位结构可以集成在功率器件的有源区域外部，例如在有源区域下方和/或衬底内部。 在功率器件的有源区域之外集成钳位结构可以使给定管芯尺寸的有效面积最大化，并且改善钳位器件的鲁棒性，因为电流将通过该积分在衬底中扩展。

公开(公告)号：US20140001588A1

公开(公告)日：2014-01-02

申请号：US13535925

申请日：2012-06-28

Applicant: Michael I-Shan Sun ,  Francois Hebert ,  Kenneth C. Dyer ,  Eric S. Lee

Inventor： Michael I-Shan Sun ,  Francois Hebert ,  Kenneth C. Dyer ,  Eric S. Lee

IPC: H01L27/14 ,  H01L31/18

CPC classification number: H01L27/14621

Abstract: Monolithic optical sensor devices, and methods for fabricating such devices, are described herein. In an embodiment, a semiconductor wafer substrate includes a plurality of photodetector (PD) regions. A wafer-level inorganic dielectric optical filter is deposited and thereby formed over at least a subset of the plurality of PD regions. One or more wafer-level organic color filter(s) is/are deposited and thereby formed on one or more selected portion(s) of the wafer-level inorganic dielectric optical filter that is/are over selected ones of the PD regions. For example, an organic red filter, an organic green filter and an organic blue filter can be over, respectively, portions of the wafer-level inorganic dielectric optical filter that are over first, second and third PD regions.

Abstract translation: 本文描述了单片光学传感器装置及其制造方法。 在一个实施例中，半导体晶片衬底包括多个光电检测器（PD）区域。 沉积晶片级无机介质光学滤波器，从而形成在多个PD区域的至少一个子集上。 沉积一个或多个晶片级有机彩色滤光片，从而在晶片级无机介质光学滤波器的一个或多个选定的部分上形成PD选择的一部分。 例如，有机红色滤色器，有机绿色滤色器和有机蓝色滤色器可以分别结束在第一，第二和第三PD区域之上的晶片级无机介质滤光器的部分。

公开(公告)号：US08492225B2

公开(公告)日：2013-07-23

申请号：US12938589

申请日：2010-11-03

Applicant: Dev Alok Girdhar ,  Francois Hebert

Inventor： Dev Alok Girdhar ,  Francois Hebert

IPC: H01L21/336

CPC classification number: H01L27/0629 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/7834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for a voltage converter including a trench field effect transistor (FET) and a trench guarded Schottky diode which is integrated with the trench FET. In an embodiment, a voltage converter can include a lateral FET, a trench FET, and a trench guarded Schottky diode integrated with the trench FET. A method to form a voltage converter can include the formation of a trench FET gate, a trench guarded Schottky diode gate, and a lateral FET gate using a single conductive layer such as a polysilicon layer.

Abstract translation: 一种电压转换器的方法和结构，包括与沟槽FET集成的沟槽场效应晶体管（FET）和沟槽保护肖特基二极管。 在一个实施例中，电压转换器可以包括横向FET，沟槽FET和与沟槽FET集成的沟槽保护肖特基二极管。 形成电压转换器的方法可以包括使用诸如多晶硅层的单个导电层形成沟槽FET栅极，沟槽保护肖特基二极管栅极和横向FET栅极。

公开(公告)号：US20130043940A1

公开(公告)日：2013-02-21

申请号：US13358718

申请日：2012-01-26

Applicant: Francois Hebert ,  Steven R. Rivet ,  Michael Althar ,  Peter Oaklander

Inventor： Francois Hebert ,  Steven R. Rivet ,  Michael Althar ,  Peter Oaklander

IPC: H01L25/16 ,  H01L23/495 ,  H01L21/50 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/3732 ,  H01L23/4334 ,  H01L23/49517 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/05553 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32145 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83855 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06589 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/10162 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/14253 ,  H01L2924/1426 ,  H01L2924/181 ,  Y10T29/49121 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.

Abstract translation: 本文公开的实施例提供了包括具有有源侧和背侧的第一管芯的电路，其中第一管芯被倒装芯片安装到载体上。 电路还包括堆叠在第一管芯的背面上的第二管芯，其中第二管芯堆叠在第一管芯上，使得第二管芯的背面面向第一管芯的背面，第二管芯的有源侧 面对远离第一个模具。

公开(公告)号：US20120256193A1

公开(公告)日：2012-10-11

申请号：US13165396

申请日：2011-06-21

Applicant: Francois Hebert ,  Stephen J. Gaul ,  Shea Petricek

Inventor： Francois Hebert ,  Stephen J. Gaul ,  Shea Petricek

IPC: H01L29/02 ,  H01L29/06 ,  H01L21/02 ,  H01L29/92

CPC classification number: H01L23/5223 ,  H01L21/823418 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0629 ,  H01L27/088 ,  H01L28/60 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/7813 ,  H01L29/7835 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00011 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor structure such as a power converter with an integrated capacitor is provided, and comprises a semiconductor substrate, a high-side output power device over the substrate at a first location, and a low-side output power device over the substrate at a second location adjacent to the first location. A first metal layer is over the high-side output power device and electrically coupled to the high-side output power device, and a second metal layer is over the low-side output power device and electrically coupled to the low-side output power device. A dielectric layer is over a portion of the first metal layer and a portion of the second metal layer, and a top metal layer is over the dielectric layer. The integrated capacitor comprises a first bottom electrode that includes the portion of the first metal layer, a second bottom electrode that includes the portion of the second metal layer, the dielectric layer over the portions of the first and second metal layers, and a top electrode that includes the top metal layer over the dielectric layer.

Abstract translation: 提供了诸如具有集成电容器的功率转换器的半导体结构，并且包括半导体衬底，在第一位置处的衬底上的高侧输出功率器件和在第二位置处的衬底上的低侧输出功率器件 位置与第一个位置相邻。 第一金属层位于高侧输出功率器件的上方并且电耦合到高侧输出功率器件，并且第二金属层在低侧输出功率器件的上方并且电耦合到低侧输出功率器件 。 电介质层位于第一金属层的一部分和第二金属层的一部分上，并且顶部金属层在电介质层的上方。 集成电容器包括包括第一金属层的部分的第一底部电极，包括第二金属层的部分的第二底部电极，第一和第二金属层的部分上的电介质层，以及顶部电极 其包括在电介质层上的顶部金属层。

公开(公告)号：US08242510B2

公开(公告)日：2012-08-14

申请号：US12946669

申请日：2010-11-15

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L29/15

CPC classification number: H01L29/7787 ,  H01L21/0242 ,  H01L21/0245 ,  H01L21/0254 ,  H01L21/02658 ,  H01L21/76281 ,  H01L21/8258 ,  H01L27/085 ,  H01L29/2003 ,  H01L29/66462

Abstract: A structure and method for a semiconductor device includes a silicon device layer and a gallium nitride (GaN) device layer. In an embodiment, the silicon device layer and the GaN device layer have upper surfaces which are coplanar with each other. In another embodiment, the GaN device layer does not directly underlie the silicon device layer, and the silicon device layer does not directly underlie the GaN device layer. The semiconductor device can further include a silicon-based semiconductor device formed on and/or within the silicon device layer, and a nitride-based semiconductor device formed on and/or within the GaN device layer. The GaN device layer can include a plurality of layers which can be formed as conformal blanket layers and then planarized, or which can be selectively formed then planarized.

Abstract translation: 半导体器件的结构和方法包括硅器件层和氮化镓（GaN）器件层。 在一个实施例中，硅器件层和GaN器件层具有彼此共面的上表面。 在另一个实施例中，GaN器件层不直接位于硅器件层之下，并且硅器件层不直接位于GaN器件层的下面。 半导体器件还可以包括形成在硅器件层上和/或内部的硅基半导体器件，以及形成在GaN器件层上和/或内部的氮化物基半导体器件。 GaN器件层可以包括可以形成为保形覆盖层然后平坦化的多个层，或者可以选择性地形成，然后进行平面化。

公开(公告)号：US08232137B2

公开(公告)日：2012-07-31

申请号：US12773275

申请日：2010-05-04

Applicant: Stephen Joseph Gaul ,  Francois Hebert

Inventor： Stephen Joseph Gaul ,  Francois Hebert

IPC: H01L21/00

CPC classification number: H01L23/3732 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/06515 ,  H01L2224/1403 ,  H01L2224/14515 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.

Abstract translation: 半导体器件组件和方法可以包括单个半导体层或层叠的半导体层，例如半导体晶片或晶片部分（半导体晶片）。 在每个半导体层上，通过其形成的金刚石层可有助于散热和散热。 金刚石层可以包括半导体层背面的第一部分和垂直延伸到半导体层中的一个或多个第二部分，例如完全穿过半导体层。 然后可以对金刚石层进行热接触以将热量从一个或多个半导体层导出。 可以通过金刚石层形成导电通孔，以提供信号路由和散热能力。