公开(公告)号：US09679615B2

公开(公告)日：2017-06-13

申请号：US13919503

申请日：2013-06-17

Applicant: Micron Technology, Inc.

Inventor： Joe M. Jeddeloh ,  Brent Keeth

IPC: G11C5/06 ,  G11C5/14 ,  G11C7/10 ,  H01L25/065 ,  G11C5/02 ,  G11C11/4063

CPC classification number: G11C5/066 ,  G11C5/025 ,  G11C5/14 ,  G11C7/10 ,  G11C11/4063 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.

公开(公告)号：US20150348956A1

公开(公告)日：2015-12-03

申请号：US14825009

申请日：2015-08-12

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijan Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L25/00 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/42 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/15311

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

Abstract translation: 本文公开了具有多个热路径和相关系统和方法的堆叠的半导体管芯组件。 在一个实施例中，半导体管芯组件可以包括布置在堆叠中的多个第一半导体管芯和承载第一半导体管芯的第二半导体管芯。 第二半导体管芯可以包括横向向外延伸超过第一半导体管芯的至少一侧的周边部分。 半导体管芯组件还可以包括在第二半导体管芯的周边部分处的热传递特征。 第一半导体管芯可以限定第一热路径，并且热转移特征可以限定与第一半导体管芯分离的第二热路径。

公开(公告)号：US20150255153A1

公开(公告)日：2015-09-10

申请号：US14719053

申请日：2015-05-21

Applicant: Micron Technology, Inc.

Inventor： D.V. Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Lei Bi ,  Adam D. Johnson ,  Brent Keeth ,  Alessandro Calderoni ,  Scott E. Sills

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057

Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

Abstract translation: 本公开包括用于感测电阻式存储单元的装置和方法。 许多实施例包括对存储器单元执行感测操作以确定与存储器单元相关联的当前值，将编程信号施加到存储器单元，以及基于与存储器单元相关联的当前值来确定存储器单元的数据状态 在施加编程信号之前应用编程信号的存储单元和与存储器单元相关联的当前值。

公开(公告)号：US20150124517A1

公开(公告)日：2015-05-07

申请号：US14588593

申请日：2015-01-02

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Durai Vishak Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Adam D. Johnson ,  Scott E. Sills ,  Alessandro Calderoni

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2013/0071 ,  G11C2013/0076 ,  G11C2013/0083 ,  H01L22/14

Abstract: Apparatus and methods of forming a memory cell are described. In one such method, a forming charge applied to a memory cell, such as a Resistive RAM (RRAM) memory cell, is monitored to determine the progress of the forming the cell. If the cell is consuming charge too slowly, a higher voltage can be applied. If the cell is consuming charge too quickly, a lower voltage can be applied. The charge may be monitored by charging a capacitor to a certain level, then monitoring the discharge rate of the capacitor though the cell. The monitoring may use comparators to measure the charge. The monitoring may also use an analog to digital converter to perform the monitoring.

Abstract translation: 描述形成存储器单元的装置和方法。 在一种这样的方法中，监视施加到诸如电阻RAM（RRAM）存储单元的存储单元的成形电荷，以确定形成单元的进程。 如果电池消耗电荷太慢，则可以施加更高的电压。 如果电池消耗电荷太快，则可以施加较低的电压。 可以通过将电容器充电到一定水平来监测电荷，然后通过电池监测电容器的放电速率。 监控可以使用比较器来测量电荷。 监视还可以使用模数转换器来执行监视。

公开(公告)号：US08929125B2

公开(公告)日：2015-01-06

申请号：US13772056

申请日：2013-02-20

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Durai Vishak Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Adam D. Johnson ,  Scott E. Sills ,  Alessandro Calderoni

IPC: G11C11/00 ,  G11C13/00 ,  H01L21/66

CPC classification number: G11C13/0069 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2013/0071 ,  G11C2013/0076 ,  G11C2013/0083 ,  H01L22/14

Abstract: Apparatuses and methods of forming a memory cell is described. In one such method, a forming charge applied to a memory cell, such as a Resistive RAM (RRAM) memory cell, is monitored to determine the progress of the forming the cell. If the cell is consuming charge too slowly, a higher voltage can be applied. If the cell is consuming charge too quickly, a lower voltage can be applied. The charge may be monitored by charging a capacitor to a certain level, then monitoring the discharge rate of the capacitor though the cell. The monitoring may use comparators to measure the charge. The monitoring may also use an analog to digital converter to perform the monitoring.

Abstract translation: 描述形成存储器单元的装置和方法。 在一种这样的方法中，监视施加到诸如电阻RAM（RRAM）存储单元的存储单元的成形电荷，以确定形成单元的进程。 如果电池消耗电荷太慢，则可以施加更高的电压。 如果电池消耗电荷太快，则可以施加较低的电压。 可以通过将电容器充电到一定水平来监测电荷，然后通过电池监测电容器的放电速率。 监控可以使用比较器来测量电荷。 监视还可以使用模数转换器来执行监视。

公开(公告)号：US20140233298A1

公开(公告)日：2014-08-21

申请号：US13772056

申请日：2013-02-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Brent Keeth ,  Durai Vishak Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Adam D. Johnson ,  Scott E. Sills ,  Alessandro Calderoni

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2013/0071 ,  G11C2013/0076 ,  G11C2013/0083 ,  H01L22/14

Abstract: Apparatuses and methods of forming a memory cell is described. In one such method, a forming charge applied to a memory cell, such as a Resistive RAM (RRAM) memory cell, is monitored to determine the progress of the forming the cell. If the cell is consuming charge too slowly, a higher voltage can be applied. If the cell is consuming charge too quickly, a lower voltage can be applied. The charge may be monitored by charging a capacitor to a certain level, then monitoring the discharge rate of the capacitor though the cell. The monitoring may use comparators to measure the charge. The monitoring may also use an analog to digital converter to perform the monitoring.

Abstract translation: 描述形成存储器单元的装置和方法。 在一种这样的方法中，监视施加到诸如电阻RAM（RRAM）存储单元的存储单元的成形电荷，以确定形成单元的进程。 如果电池消耗电荷太慢，则可以施加更高的电压。 如果电池消耗电荷太快，则可以施加较低的电压。 可以通过将电容器充电到一定水平来监测电荷，然后通过电池监测电容器的放电速率。 监控可以使用比较器来测量电荷。 监视还可以使用模数转换器来执行监视。

公开(公告)号：US20240256473A1

公开(公告)日：2024-08-01

申请号：US18630400

申请日：2024-04-09

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Frank F Ross ,  Richard C Murphy

IPC: G06F13/16 ,  G06N3/004 ,  H01L25/065 ,  H01L25/18

CPC classification number: G06F13/1668 ,  G06N3/004 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06562

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a stack of memory dies, a controller die, and a buffer. Example memory devices, systems and methods include one or more neuromorphic layers logically coupled between one or more dies in the stack of memory dies and a host interface of the controller die.

公开(公告)号：US20240237363A1

公开(公告)日：2024-07-11

申请号：US18400994

申请日：2023-12-29

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth ,  Ameen D. Akel ,  Kunal R. Parekh ,  Amy Rae Griffin ,  Eiichi Nakano

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: Methods, systems, and devices for modular die configurations for multi-channel memory are described. A semiconductor component (e.g., a semiconductor wafer) may be configured with multiple rows and multiple columns of memory arrays, and associated channels. A row of memory arrays may be associated with a contact region extending along the row direction. The semiconductor component may also include control regions extending along the column direction between at least some of the columns of memory arrays. Each control region may include control circuitry for operating memory arrays on one or both sides of the control region. The channels and memory arrays of the semiconductor wafer may be grouped into one or more independently-operable memory dies, with each memory die having at least a portion of a control region and at least a portion of a contact region for operating the memory arrays of the memory die.

公开(公告)号：US20240070069A1

公开(公告)日：2024-02-29

申请号：US18215474

申请日：2023-06-28

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

IPC: G06F12/06 ,  G06F12/02 ,  G11C11/4093 ,  G11C29/12 ,  H01L25/065 ,  H01L25/18

CPC classification number: G06F12/0653 ,  G06F12/0215 ,  G11C11/4093 ,  G11C29/12 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  G06F2212/1016 ,  G11C2211/4062 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

公开(公告)号：US11791317B2

公开(公告)日：2023-10-17

申请号：US18048732

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth

IPC: H01L25/065 ,  H01L27/02 ,  H01L23/00 ,  H01L27/118

CPC classification number: H01L25/0657 ,  H01L27/0207 ,  H01L24/16 ,  H01L2027/11838 ,  H01L2224/05548 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/17106 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1436 ,  H01L2924/1441

Abstract: Systems, apparatuses, and methods related to dynamic random access memory (DRAM), such as finer grain DRAM, are described. For example, an array of memory cells in a memory device may be partitioned into regions. Each region may include a plurality of banks of memory cells. Each region may be associated with a data channel configured to communicate with a host device. In some examples, each channel of the array may include two or more data pins. The ratio of data pins per channel may be two or four in various examples. Other examples may include eight data pins per channel.