Method of forming a topside contact to a backside terminal of a semiconductor device
    83.
    发明授权
    Method of forming a topside contact to a backside terminal of a semiconductor device 有权
    在半导体器件的背面端子上形成顶部接触的方法

    公开(公告)号:US08536042B2

    公开(公告)日:2013-09-17

    申请号:US12982509

    申请日:2010-12-30

    IPC分类号: H01L21/44

    摘要: A process for forming a vertically conducting semiconductor device includes providing a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. The process also includes forming an epitaxial layer extending over the topside surface of the semiconductor substrate but terminating prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. The method also includes forming an interconnect layer extending into the recessed region but terminating prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.

    摘要翻译: 形成垂直导电半导体器件的工艺包括提供具有顶侧表面和背面的半导体衬底。 半导体衬底用作垂直传导器件的端子,用于在操作期间偏压垂直传导器件。 该工艺还包括形成在半导体衬底的顶侧表面上延伸但在到达半导体衬底的边缘之前终止的外延层,以沿着半导体衬底的周边形成凹陷区域。 该方法还包括形成延伸到凹陷区域中但在到达半导体衬底的边缘之前终止的互连层。 互连层在凹陷区域中电接触半导体衬底的顶侧表面,从而提供与半导体衬底的顶侧接触。

    High voltage semiconductor device with JFET regions containing dielectrically isolated junctions and method of fabricating the same
    87.
    发明授权
    High voltage semiconductor device with JFET regions containing dielectrically isolated junctions and method of fabricating the same 有权
    具有包含介电隔离结的JFET区域的高电压半导体器件及其制造方法

    公开(公告)号:US08148758B2

    公开(公告)日:2012-04-03

    申请号:US12928682

    申请日:2010-12-16

    申请人: Hamza Yilmaz

    发明人: Hamza Yilmaz

    IPC分类号: H01L29/72

    摘要: A high-voltage field-effect device contains an extended drain or “drift” region including an embedded stack of JFET regions separated by intervening layers of the drift region. Each of the JFET regions is filled with material of an opposite conductivity type to that of the drift region, and the floor and ceiling of each JFET region is lined with an oxide layer. When the device is blocking a voltage in the off condition, the semiconductor material inside the JFET regions and in the drift region that separates the JFET regions is depleted. This improves the voltage-blocking ability of the device while conserving chip area. The oxide layer prevents dopant from the JFET regions from diffusing into the drift region.

    摘要翻译: 高电压场效应器件包含延伸的漏极或“漂移”区域,包括由漂移区的中间层隔开的JFET区域的嵌入堆叠。 每个JFET区域都填充有与漂移区域相反的导电类型的材料,并且每个JFET区域的地板和天花板都衬有氧化物层。 当器件在断开状态下阻塞电压时,JFET区域内部和分离JFET区域的漂移区域内的半导体材料耗尽。 这提高了器件的压阻能力,同时节省了芯片面积。 氧化物层防止来自JFET区域的掺杂剂扩散到漂移区域。

    METHOD AND STRUCTURE FOR DIVIDING A SUBSTRATE INTO INDIVIDUAL DEVICES
    88.
    发明申请
    METHOD AND STRUCTURE FOR DIVIDING A SUBSTRATE INTO INDIVIDUAL DEVICES 有权
    将基板分解成个体设备的方法和结构

    公开(公告)号:US20110201179A1

    公开(公告)日:2011-08-18

    申请号:US13095584

    申请日:2011-04-27

    IPC分类号: H01L21/78

    CPC分类号: H01L21/78

    摘要: A method for obtaining individual dies from a semiconductor structure is disclosed. The semiconductor structure includes a device layer, and the device layer in turn includes active regions separated by predefined spacings. Thick metal is selectively formed on backside of the device layer such that thick metal is formed on backside of active regions but not on backside of the predefined spacings. The semiconductor structure is then cut along the predefined spacings to separate the active regions with thick metal on their backside into individual dies.

    摘要翻译: 公开了一种从半导体结构获得单个管芯的方法。 半导体结构包括器件层,器件层又包括由预定间隔隔开的有源区。 在器件层的背侧选择性地形成厚金属,使得在有源区的背面形成厚金属,而不在预定间隔的背面形成厚金属。 然后沿着预定的间隔切割半导体结构,以将其背面的厚金属的活性区域分离成单独的管芯。

    Power Device with Improved Edge Termination
    89.
    发明申请
    Power Device with Improved Edge Termination 有权
    具有改进的边缘终止的电源设备

    公开(公告)号:US20110089488A1

    公开(公告)日:2011-04-21

    申请号:US12982051

    申请日:2010-12-30

    IPC分类号: H01L29/78 H01L21/768

    摘要: A field effect transistor includes an active region and a termination region surrounding the active region. A resistive element is coupled to the termination region, wherein upon occurrence of avalanche breakdown in the termination region an avalanche current starts to flow in the termination region, and the resistive element is configured to induce a portion of the avalanche current to flow through the termination region and a remaining portion of the avalanche current to flow through the active region.

    摘要翻译: 场效应晶体管包括有源区和围绕有源区的端接区。 电阻元件耦合到终端区域,其中当在终止区域中出现雪崩击穿时,雪崩电流开始在终止区域中流动,并且电阻元件被配置为诱导雪崩电流的一部分流过终端 区域和雪崩电流的剩余部分流过有源区域。