公开(公告)号：US09443824B1

公开(公告)日：2016-09-13

申请号：US14673435

申请日：2015-03-30

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Jae Sik Lee ,  Dong Wook Kim

IPC: H01L23/02 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32137 ,  H01L2224/81192 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/381 ,  H01L2924/00014

Abstract: An integrated circuit (IC) package structure may include a substrate. The substrate may include a semiconductor bridge having a first surface directly on a surface of the substrate that faces a first semiconductor die and a second semiconductor die. The semiconductor bridge may be disposed within a cavity extending through a photo-sensitive layer on the surface of the substrate. The semiconductor bridge may have an exposed, second surface substantially flush with the photo-sensitive layer. The first semiconductor die and the second semiconductor die are supported by the substrate and coupled together through the semiconductor bridge.

Abstract translation: 集成电路（IC）封装结构可以包括衬底。 衬底可以包括半导体电桥，其具有直接位于衬底的面向第一半导体管芯和第二半导体管芯的表面上的第一表面。 半导体桥可以设置在延伸穿过衬底表面上的光敏层的空腔内。 半导体桥可以具有基本上与光敏层齐平的暴露的第二表面。 第一半导体管芯和第二半导体管芯由衬底支撑并通过半导体桥耦合在一起。

公开(公告)号：US09385077B2

公开(公告)日：2016-07-05

申请号：US14329646

申请日：2014-07-11

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook Kim ,  Young Kyu Song ,  Kyu-Pyung Hwang ,  Hong Bok We

IPC: H01L21/44 ,  H01L23/498 ,  H01L21/48 ,  H05K1/02 ,  H05K3/28 ,  H05K3/46

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/19107 ,  H05K1/0298 ,  H05K3/284 ,  H05K3/46 ,  H05K2203/1316

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first interconnect coupled to the substrate, and a second interconnect surrounding the first interconnect. The second interconnect may be configured to provide an electrical connection to ground. In some implementations, the second interconnect includes a plate. In some implementations, the integrated device also includes a dielectric material between the first interconnect and the second interconnect. In some implementations, the integrated device also includes a mold surrounding the second interconnect. In some implementations, the first interconnect is configured to conduct a power signal in a first direction. In some implementations, the second interconnect is configured to conduct a grounding signal in a second direction. In some implementations, the second direction is different from the first direction. In some implementations, the integrated device may be a package-on-package (PoP) device.

Abstract translation: 一些新颖的特征涉及包括衬底，耦合到衬底的第一互连和围绕第一互连的第二互连的集成器件。 第二互连可以被配置为提供到地的电连接。 在一些实现中，第二互连包括板。 在一些实施方案中，集成器件还包括在第一互连和第二互连之间的介电材料。 在一些实施方案中，集成装置还包括围绕第二互连的模具。 在一些实现中，第一互连被配置为在第一方向上传导功率信号。 在一些实现中，第二互连被配置为在第二方向上传导接地信号。 在一些实施方式中，第二方向与第一方向不同。 在一些实施方式中，集成器件可以是封装封装（PoP）器件。

公开(公告)号：US09355963B2

公开(公告)日：2016-05-31

申请号：US14498076

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook Kim ,  Jae Sik Lee ,  Hong Bok We ,  Young Kyu Song ,  Chin-Kwan Kim ,  Kyu-Pyung Hwang ,  Shiqun Gu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8203 ,  H01L2224/92124 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00

Abstract: A semiconductor package according to some examples of the disclosure may include a base with a first redistribution layer on one side, first and second side by side die attached to the base on an opposite side from the first redistribution layer, an interposer attached to active sides of the first and second die to provide an interconnection between the first and second die, a plurality of die vias extending from the first and second die to a second redistribution layer on a surface of the package opposite the first redistribution layer, and a plurality of package vias extending through the package between the first and second redistribution layers.

Abstract translation: 根据本公开的一些示例的半导体封装可以包括在一侧具有第一再分布层的基底，在与第一再分布层相反的一侧上附接到基部的第一和第二并排裸片，附接到主动侧的插入件 以提供第一和第二管芯之间的互连，从第一和第二管芯延伸到在与第一再分布层相对的封装的表面上的第二再分配层的多个管芯通孔，以及多个 在第一和第二再分配层之间延伸穿过包装的通孔。

公开(公告)号：US20160091532A1

公开(公告)日：2016-03-31

申请号：US14498291

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Hong Bok We ,  Dong Wook Kim ,  Chin-Kwan Kim ,  Jae Sik Lee ,  Kyu-Pyung Hwang ,  Seung Hyuk Kang

IPC: G01R1/073 ,  H01L21/66 ,  H01L21/48 ,  G01R31/28

CPC classification number: G01R1/0735 ,  G01R1/07378 ,  G01R31/2887 ,  H01L21/4853 ,  H01L21/4857 ,  H01L22/30

Abstract: Flexible film electrical-test substrates with at least one conductive contact post for integrated circuit (IC) bump(s) electrical testing, and related methods and testing apparatuses are disclosed. The backside structure of an electrical-test substrate comprises a flexible dielectric film structure. One or more fine-pitched conductive coupling posts are formed on conductive pads disposed on a front side of the flexible dielectric film structure through a fabrication process. A first pitch of the conductive coupling post(s) in the flexible dielectric film structure is provided to be the same or substantially the same as a second pitch of one or more bumps in an IC, such as die or interposer (e.g., forty (40) micrometers (μm) or less). This allows the conductive coupling post(s) to be placed into mechanical contact with at least one bump of the IC, point-by-point, during an electrical test to electrically testing of the IC.

Abstract translation: 公开了具有至少一个用于集成电路（IC）凸点电气测试的导电接触柱的柔性膜电测基板，以及相关方法和测试装置。 电测基板的背面结构包括柔性介电膜结构。 通过制造工艺，在设置在柔性电介质膜结构的前侧的导电焊盘上形成一个或多个细间距导电耦合柱。 将柔性电介质膜结构中的导电耦合柱的第一间距设置成与IC中的一个或多个凸起的第二间距相同或基本相同，例如模具或插入件（例如，40（ 40微米（μm）以下）。 这允许导电耦合柱在电测试期间被放置成与IC的至少一个凸点相接触，以电IC测试。

公开(公告)号：US20160049378A1

公开(公告)日：2016-02-18

申请号：US14462265

申请日：2014-08-18

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Hong Bok We ,  Dong Wook Kim ,  Kyu-Pyung Hwang

IPC: H01L23/00 ,  H01L23/367

CPC classification number: H01L24/17 ,  H01L21/4857 ,  H01L23/34 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/10175 ,  H01L2224/131 ,  H01L2224/16111 ,  H01L2224/16112 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/17519 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83104 ,  H05K1/0207 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Provided herein is an integrated device that includes a substrate, a die, a heat-dissipation layer located between the substrate and the die, and a first interconnect configured to couple the die to the heat-dissipation layer. The heat-dissipation layer may be configured to provide an electrical path for a ground signal. The first interconnect may be further configured to conduct heat from the die to the heat-dissipation layer. The integrated device may also include a second interconnect configured to couple the die to the substrate. The second interconnect may be further configured to conduct a power signal between the die and the substrate. The integrated device may also include a dielectric layer located between the heat-dissipation layer and the substrate, and a solder-resist layer located between the die and the heat-dissipation layer.

Abstract translation: 本文提供了一种集成器件，其包括衬底，管芯，位于衬底和管芯之间的散热层和被配置为将管芯耦合到散热层的第一互连。 散热层可以被配置成为接地信号提供电路径。 第一互连可以被进一步配置成将热量从管芯传导到散热层。 集成器件还可以包括配置成将管芯耦合到衬底的第二互连。 第二互连可以被进一步配置为在管芯和衬底之间传导功率信号。 集成器件还可以包括位于散热层和衬底之间的介电层，以及位于管芯和散热层之间的阻焊层。

公开(公告)号：US20150257282A1

公开(公告)日：2015-09-10

申请号：US14196481

申请日：2014-03-04

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Jae Sik Lee ,  Shiqun Gu

IPC: H05K3/42 ,  H05K1/11 ,  H05K3/00 ,  H05K1/03

CPC classification number: H05K3/426 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L2224/18 ,  H05K1/0306 ,  H05K1/0313 ,  H05K1/111 ,  H05K1/115 ,  H05K3/0094

Abstract: A substrate includes a plurality of vias that are lined with dielectric polymer having a substantially uniform thickness. This substantial uniform thickness provides a lumen within each dielectric-polymer-layer-lined via that is substantially centered within the via. Subsequent deposition of metal into the lumen for each dielectric-polymer-layer-lined via thus provides conductive vias having substantially centered metal conductors.

Abstract translation: 衬底包括多个具有基本上均匀厚度的介电聚合物的通孔。 这个基本上均匀的厚度提供了在每个介质聚合物层衬里的通孔内的管腔，其基本上位于通孔内。 因此，随后将金属沉积到每个介质聚合物层衬里的通孔的内腔中，由此提供具有基本中心的金属导体的导电通孔。

公开(公告)号：US20150255416A1

公开(公告)日：2015-09-10

申请号：US14196817

申请日：2014-03-04

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook Kim ,  Hong Bok We ,  Jae Sik Lee ,  Shiqun Gu

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24137 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1815 ,  H01L2924/014

Abstract: Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die coupled to a first surface of the base portion, and an underfill between the first die and the base portion. The base portion includes a dielectric layer, and a set of redistribution metal layers. In some implementations, the integrated device further includes an encapsulation material that encapsulates the first die. In some implementations, the integrated device further includes a second die coupled to the first surface of the base portion. In some implementations, the integrated device further includes a set of interconnects on the base portion, the set of interconnects electrically coupling the first die and the second die. In some implementations, the first die includes a first set of interconnect pillars and the second die includes a second set of interconnect pillars.

Abstract translation: 一些新颖的特征涉及一种集成器件（例如，集成封装），其包括用于集成器件的基座部分，耦合到基部部分的第一表面的第一管芯以及第一管芯和基部之间的底部填充。 基部包括电介质层和一组再分布金属层。 在一些实施方案中，集成器件还包括封装第一裸片的封装材料。 在一些实施方案中，集成装置还包括耦合到基部的第一表面的第二模具。 在一些实施方案中，集成器件还包括在基部上的一组互连，该组互连电耦合第一管芯和第二管芯。 在一些实施方案中，第一管芯包括第一组互连柱，并且第二管芯包括第二组互连柱。

公开(公告)号：US20250079281A1

公开(公告)日：2025-03-06

申请号：US18458242

申请日：2023-08-30

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Joan Rey Villarba Buot ,  Sang-Jae Lee ,  Zhijie Wang ,  Michelle Yejin Kim

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

Abstract: Hybrid package substrates employing film metallization layers with outer pre-impregnated (PPG) region(s) to support high density bump and wire bond connections for respective bump and wire bond connected dies in the IC package, and related hybrid integrated circuit (IC) packages and fabrication methods are disclosed. The package substrate includes film metallization layers of a softer, flexible material that can more easily be patterned to support formation of high density, reduced pitch metal interconnects to support finer bump pitch connections to a bottom, first die(s) in a die region of the package substrate. The package substrate also includes one or more PPG regions a PPG metallization layer(s) adjacent to the die region of the package substrate that reinforces the film metallization layers and also supports the formation of wire bond pads for wire bond connections to an upper, second die(s) in the hybrid IC package.

公开(公告)号：US20250062235A1

公开(公告)日：2025-02-20

申请号：US18450636

申请日：2023-08-16

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba Buot ,  Hong Bok We ,  Zhijie Wang ,  Sang-Jae Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/16

Abstract: Package substrate with metallization layer(s) that includes an additional metal pad layer to facilitate reduced via size for reduced bump pitch, and related integrated circuit (IC) packages and fabrication methods. An additional metal pad(s) is provided in an insulating layer of a metallization layer(s) of the package substrate in which a via(s) is formed to reduce vertical connectivity distance between metal interconnects in adjacent metallization layers electrically coupled together by the via. This can reduce the aspect ratio and size of the via thereby allowing metal interconnects that are electrically coupled to the via to also be reduced in size (e.g., width) while still supporting an aligned, low resistance connection between the via(s) and the metal interconnects. Being able to reduce the size (e.g., width) of the metal interconnects can reduce bump pitch of the package substrate, which can facilitate a higher density of die/bump connections to the package substrate.

公开(公告)号：US12230552B2

公开(公告)日：2025-02-18

申请号：US17455576

申请日：2021-11-18

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Joan Rey Villarba Buot ,  Aniket Patil

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498

Abstract: Disclosed is a stack via structure in which a plurality of vias are stacked over each other. At least one via is a via that has a recess formed from a top surface thereof. Another via above the via is formed such that a bottom portion of the another via is in the recess of the via. In this way, no capture pad is needed between the via and the another via. Also, contact area between the via and the another via is enhanced.