Multi-level stacked transistor device including capacitor and different semiconductor materials

    公开(公告)号:US09755084B2

    公开(公告)日:2017-09-05

    申请号:US13755921

    申请日:2013-01-31

    CPC classification number: H01L29/78693 H01L27/1225 H01L27/1255

    Abstract: A semiconductor device having a novel structure is provided in which a transistor including an oxide semiconductor and a transistor including a semiconductor material which is not an oxide semiconductor are stacked. Further, a semiconductor device in which a semiconductor element and a capacitor are formed efficiently is provided. In a semiconductor device, a first semiconductor element layer including a transistor formed using a semiconductor material which is not an oxide semiconductor, such as silicon, and a second semiconductor element layer including a transistor formed using an oxide semiconductor are stacked. A capacitor is formed using a wiring layer, or a conductive film or an insulating film which is in the same layer as a conductive film or an insulating film of the second semiconductor element layer.

    Semiconductor device having a gate insulting film with thick portions aligned with a tapered gate electrode
    87.
    发明授权
    Semiconductor device having a gate insulting film with thick portions aligned with a tapered gate electrode 有权
    具有栅极绝缘膜的半导体器件,其厚度与锥形栅电极对准

    公开(公告)号:US09576981B2

    公开(公告)日:2017-02-21

    申请号:US14147799

    申请日:2014-01-06

    Abstract: By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer.

    Abstract translation: 通过根据电路所要求的功能,在半导体器件的各种电路中设置适当的TFT结构,可以提高半导体器件的工作性能和可靠性,降低功耗并降低制造成本 并通过减少处理步骤的数量来提高产量。 TFT的LDD区域形成为具有用于控制导电性的杂质元素的浓度梯度,该杂质元素随着与漏极区的距离减小而变高。 为了形成具有杂质元素的浓度梯度的这样的LDD区域,本发明使用了具有锥形部的栅电极的方法,从而掺杂电离杂质元素,以控制在电场中加速的电导率,从而 其穿过栅电极和栅绝缘膜进入半导体层。

    Photoelectric conversion device and manufacturing method thereof
    88.
    发明授权
    Photoelectric conversion device and manufacturing method thereof 有权
    光电转换装置及其制造方法

    公开(公告)号:US09450132B2

    公开(公告)日:2016-09-20

    申请号:US14514552

    申请日:2014-10-15

    Abstract: An object is to increase conversion efficiency of a photoelectric conversion device without increase in the manufacturing steps. The photoelectric conversion device includes a first semiconductor layer formed using a single crystal semiconductor having one conductivity type which is formed over a supporting substrate, a buffer layer including a single crystal region and an amorphous region, a second semiconductor layer which includes a single crystal region and an amorphous region and is provided over the butler layer, and a third semiconductor layer having a conductivity type opposite to the one conductivity type, which is provided over the second semiconductor layer. A proportion of the single crystal region is higher than that of the amorphous region on the first semiconductor layer side in the second semiconductor layer, and the proportion of the amorphous region is higher than that of the single crystal region on the third semiconductor layer side.

    Abstract translation: 目的在于提高光电转换装置的转换效率,而不增加制造步骤。 光电转换装置包括使用在支撑基板上形成的具有一种导电类型的单晶半导体形成的第一半导体层,包括单晶区域和非晶区域的缓冲层,包括单晶区域的第二半导体层 和非晶区域,并且设置在管状层上方,以及设置在第二半导体层上的具有与一种导电类型相反的导电类型的第三半导体层。 单晶区域的比例高于第二半导体层中的第一半导体层侧的非晶区域的比例,并且非晶区域的比例高于第三半导体层侧的单晶区域的比例。

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