公开(公告)号：US20060091554A1

公开(公告)日：2006-05-04

申请号：US11311546

申请日：2005-12-19

申请人： Wei Pan ,  Yoshi Ono ,  David Evans ,  Sheng Hsu

发明人： Wei Pan ,  Yoshi Ono ,  David Evans ,  Sheng Hsu

IPC分类号： H01L23/48

CPC分类号： H01L21/28562 ,  H01L21/76841 ,  H01L2221/1078

摘要： A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.

摘要翻译： 通过原子层化学气相沉积（ALCVD）将多层阻挡金属薄膜沉积在衬底上。 多层膜可以包括单个化学物质的几个不同层，或者各个不同的或交替的化学物质的几个层。 在优选实施例中，多层阻挡薄膜包括在衬底上的氮化钽层，其上沉积有氮化钛层。 整个多层膜的厚度可以是大约50埃。 当与通过常规化学气相沉积（CVD）沉积的膜相比时，该膜具有优异的膜特性，例如抗扩散能力，低电阻率，高密度和台阶覆盖。 本发明的多层阻挡金属薄膜具有改善的粘合特性，特别适用于其上的铜膜的金属化。

公开(公告)号：US20060088993A1

公开(公告)日：2006-04-27

申请号：US11013804

申请日：2004-12-15

申请人： Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff ,  Sheng Hsu

发明人： Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff ,  Sheng Hsu

IPC分类号： H01L21/4763 ,  H01L21/302

CPC分类号： H01L21/31111 ,  B81C1/00111 ,  B82Y10/00

摘要： A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas of the second region exposed by the non-continuous IrOx film; and, lifting off the IrOx nanostructures overlying the second region. Typically, the first region is formed from a first material and the second region from a second material, different than the first material. For example, the first material can be a refractory metal, or refractory metal oxide. The second material can be SiOx. The step of selectively etching areas of the second region exposed by the non-continuous IrOx film includes exposing the substrate to an etchant that is more reactive with the second material than the IrOx.

摘要翻译： 提供了用于构图氧化铱（IrOx）纳米结构的方法。 该方法包括：在第二区域附近形成衬底第一区域; 从覆盖第一区域的连续IrOx膜生长IrOx纳米结构; 同时从覆盖第二区域的非连续IrOx膜生长IrOx纳米结构; 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域; 并提升覆盖第二区域的IrOx纳米结构。 通常，第一区域由第一材料形成，第二区域由不同于第一材料的第二材料形成。 例如，第一种材料可以是难熔金属或难熔金属氧化物。 第二种材料可以是SiOx。 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域的步骤包括将衬底暴露于与IrOx比第二材料更具反应性的蚀刻剂。

公开(公告)号：US20060086314A1

公开(公告)日：2006-04-27

申请号：US10971330

申请日：2004-10-21

申请人： Fengyan Zhang ,  Robert Barrowcliff ,  Sheng Hsu

发明人： Fengyan Zhang ,  Robert Barrowcliff ,  Sheng Hsu

IPC分类号： C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC分类号： H01L24/48 ,  C30B25/005 ,  C30B29/16 ,  C30B29/62 ,  H01L24/45 ,  H01L24/49 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/43827 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45178 ,  H01L2224/45181 ,  H01L2224/45565 ,  H01L2224/45599 ,  H01L2224/45688 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48599 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/14 ,  H01L2924/20751 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/811 ,  H01L2924/00014 ,  H01L2924/20651 ,  H01L2924/00 ,  H01L2924/01006

摘要： Iridium oxide (IrOx) nanowires and a method forming the nanowires are provided. The method comprises: providing a growth promotion film with non-continuous surfaces, having a thickness in the range of 0.5 to 5 nanometers (nm), and made from a material such as Ti, Co, Ni, Au, Ta, polycrystalline silicon (poly-Si), SiGe, Pt, Ir, TiN, or TaN; establishing a substrate temperature in the range of 200 to 600 degrees C.; introducing oxygen as a precursor reaction gas; introducing a (methylcyclopentadienyl)(1,5-cyclooctadiene)iridium(I) precursor; using a metalorganic chemical vapor deposition (MOCVD) process, growing IrOx nanowires from the growth promotion film surfaces. The IrOx nanowires have a diameter in the range of 100 to 1000 Å, a length in the range of 1000 Å to 2 microns, an aspect ratio (length to width) of greater than 50:1. Further, the nanowires include single-crystal nanowire cores covered with an amorphous layer having a thickness of less than 10 Å.

摘要翻译： 提供氧化铱（IrOx）纳米线和形成纳米线的方法。 该方法包括：提供具有0.5至5纳米（nm）范围内的厚度的非连续表面的生长促进膜，并由诸如Ti，Co，Ni，Au，Ta，多晶硅 多晶硅），SiGe，Pt，Ir，TiN或TaN; 建立200〜600℃的基板温度。 引入氧气作为前体反应气体; 引入（甲基环戊二烯基）（1,5-环辛二烯）铱（I）前体; 使用金属有机化学气相沉积（MOCVD）工艺，从生长促进膜表面生长IrOx纳米线。 IrOx纳米线的直径在100至1000埃的范围内，长度在1000埃至2微米之间，纵横比（长宽比）大于50:1。 此外，纳米线包括覆盖有厚度小于Å的非晶层的单晶纳米线芯。

公开(公告)号：US20060073706A1

公开(公告)日：2006-04-06

申请号：US10958537

申请日：2004-10-04

申请人： Tingkai Li ,  Sheng Hsu ,  Bruce Ulrich ,  Mark Burgholzer ,  Ray Hill

发明人： Tingkai Li ,  Sheng Hsu ,  Bruce Ulrich ,  Mark Burgholzer ,  Ray Hill

IPC分类号： H01L21/302

CPC分类号： H01L21/31116 ,  H01L29/6684 ,  H01L29/78391

摘要： A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture could increase the etch rate for the silicon nitride while reducing the etch rate for the conductive oxide, resulting in improving etch selectivity. The disclosed selective etch process is well suited for ferroelectric memory device fabrication using conductive oxide/ferroelectric interface having silicon nitride as the encapsulated material for the ferroelectric.

摘要翻译： 描述了一种干蚀刻工艺，用于从用于半导体制造工艺的导电氧化物材料中选择性地蚀刻氮化硅。 在蚀刻气体混合物中添加氧化剂可以增加氮化硅的蚀刻速率，同时降低导电氧化物的蚀刻速率，从而提高蚀刻选择性。 所公开的选择性蚀刻工艺非常适合于使用具有氮化硅作为铁电体的封装材料的导电氧化物/铁电界面的铁电存储器件制造。

公开(公告)号：US20060068509A1

公开(公告)日：2006-03-30

申请号：US11262545

申请日：2005-10-28

申请人： Sheng Hsu ,  Fengyan Zhang ,  Tingkai Li

发明人： Sheng Hsu ,  Fengyan Zhang ,  Tingkai Li

IPC分类号： H01L21/00

CPC分类号： H01L27/1159 ,  H01L21/84 ,  H01L27/11502 ,  H01L27/11585

摘要： An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.

公开(公告)号：US20060067104A1

公开(公告)日：2006-03-30

申请号：US10957298

申请日：2004-09-30

申请人： Sheng Hsu

发明人： Sheng Hsu

IPC分类号： G11C11/00

CPC分类号： G11C13/0011

摘要： A complementary resistive memory structure is provided comprising a common source electrode and a first electrode separated from the common source electrode by resistive memory material; and a second electrode adjacent to the first electrode and separated from the common source electrode by resistive memory material, along with accompanying circuitry and methods of programming and reading the complementary resistive memory structure.

摘要翻译： 提供了一种互补电阻存储器结构，其包括公共源电极和通过电阻式存储器材料与公共源电极分离的第一电极; 以及与第一电极相邻并且通过电阻性存储器材料与公共源电极分离的第二电极，以及编程和读取互补电阻性存储器结构的附带电路和方法。

公开(公告)号：US20060017488A1

公开(公告)日：2006-01-26

申请号：US10895513

申请日：2004-07-21

申请人： Sheng Hsu

发明人： Sheng Hsu

IPC分类号： H03L5/00

CPC分类号： G11C13/0007 ,  G11C13/0004 ,  G11C2213/31 ,  H01L27/0802

摘要： Using programmable resistance material for a matching resistor, a resistor trimming circuit is designed to reversibly trim a matching resistor to match a reference resistor. The programmable resistance materials such as metal-amorphous silicon metal materials, phase change materials or perovskite materials are typically used in resistive memory devices and have the ability to change the resistance reversibly and repeatable with applied electrical pulses. The present invention reversible resistor trimming circuit comprises a resistance bridge network of a matching resistor and a reference resistor to provide inputs to a comparator circuit which generates a comparing signal indicative of the resistance difference. This comparing signal can be used to control a feedback circuit to provide appropriate electrical pulses to the matching resistor to modify the resistance of the matching resistor to match that of the reference resistor.

公开(公告)号：US20050199935A1

公开(公告)日：2005-09-15

申请号：US10801375

申请日：2004-03-15

申请人： Fengyan Zhang ,  Sheng Hsu

发明人： Fengyan Zhang ,  Sheng Hsu

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L28/55 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65 ,  H01L28/75

摘要： A method is provided for forming a single-phase c-axis PGO film overlying a Pt metal electrode. Although the method is summarized in the context of a Pt bottom electrode, it has a broader application to other noble metals. The method comprises: forming a bottom electrode mixture of Pt and Pt3O4; forming a single-phase c-axis PGO thin film overlying the bottom electrode; and, forming a top electrode overlying the PGO thin film. Forming a bottom electrode mixture of a Pt and Pt3O4 includes: forming a Pt first layer; and, forming a second layer, interposed between the first layer and the PGO thin film, of fully oxidized Pt3O4. In other aspects, forming a bottom electrode mixture of Pt and Pt3O4 includes forming a polycrystalline mixture of Pt and Pt3O4. A c-axis PGO film capacitor is also provided. Again, a Pt bottom electrode is described, along with other noble metal bottom electrodes.

摘要翻译： 提供了用于形成覆盖在Pt金属电极上的单相c轴PGO膜的方法。 虽然该方法在Pt底部电极的上下文中总结，但是其更适用于其它贵金属。 该方法包括：形成Pt和Pt 3 O 4的底部电极混合物; 形成覆盖在底部电极上的单相c轴PGO薄膜; 并且形成覆盖PGO薄膜的顶部电极。 形成Pt和Pt 3 N 4 O 4的底部电极混合物包括：形成Pt第一层; 并且形成介于第一层和PGO薄膜之间的完全氧化的Pt 3 O 4 O 4的第二层。 在其它方面，形成Pt和Pt 3 O 4的底部电极混合物包括形成Pt和Pt 3 O 3的多晶混合物 > 4 。 还提供了一个c轴PGO薄膜电容器。 同样地，描述了Pt底部电极以及其它贵金属底部电极。

公开(公告)号：US20050136602A1

公开(公告)日：2005-06-23

申请号：US11039536

申请日：2005-01-19

申请人： Sheng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

发明人： Sheng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

IPC分类号： H01L21/76 ,  G11C13/00 ,  H01L21/3205 ,  H01L21/8246 ,  H01L23/52 ,  H01L27/10 ,  H01L27/105 ,  H01L27/24 ,  H01L43/08 ,  H01L29/02 ,  H01L21/336 ,  H01L21/4763 ,  H01L47/00

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/77 ,  H01L27/101 ,  H01L27/24

摘要： A memory array dual-trench isolation structure and a method for forming the same have been provided. The method comprises: forming a p-doped silicon (p-Si) substrate; forming an n-doped (n+) Si layer overlying the p-Si substrate; prior to forming the n+ Si bit lines, forming a p+ Si layer overlying the n+ Si layer; forming a layer of silicon nitride overlying the p+ layer; forming a top oxide layer overlying the silicon nitride layer; performing a first selective etch of the top oxide layer, the silicon nitride layer, the p+ Si layer, and a portion of the n+ Si layer, to form n+ Si bit lines and bit line trenches between the bit lines; forming an array of metal bottom electrodes overlying a plurality of n-doped silicon (n+ Si) bit lines, with intervening p-doped (p+) Si areas; forming a plurality of word line oxide isolation structures orthogonal to and overlying the n+ Si bit lines, adjacent to the bottom electrodes, and separating the p+ Si areas; forming a plurality of top electrode word lines, orthogonal to the n+ Si bit lines, with an interposing memory resistor material overlying the bottom electrodes; and, forming oxide-filled word line trenches adjacent the word lines.

摘要翻译： 已经提供了存储器阵列双沟槽隔离结构及其形成方法。 该方法包括：形成p掺杂硅（p-Si）衬底; 形成覆盖p-Si衬底的n掺杂（n +）Si层; 在形成n + Si位线之前，形成覆盖n + Si层的p + Si层; 形成覆盖p +层的氮化硅层; 形成覆盖所述氮化硅层的顶部氧化物层; 执行顶部氧化物层，氮化硅层，p + Si层和n + Si层的一部分的第一选择性蚀刻，以在位线之间形成n + Si位线和位线沟槽; 形成覆盖多个n掺杂硅（n + Si）位线的金属底部电极阵列，具有中间p掺杂（p +）Si区域; 形成与所述n + Si位线正交并覆盖与所述底部电极相邻并分离所述p + Si区域的多个字线氧化物隔离结构; 形成与n + Si位线正交的多个顶部电极字线，覆盖在底部电极上的插入式存储电阻材料; 并且在字线附近形成氧化物填充的字线沟槽。

公开(公告)号：US20050133723A1

公开(公告)日：2005-06-23

申请号：US10746952

申请日：2003-12-23

申请人： Jong Lee ,  Jer-Shen Maa ,  Douglas Tweet ,  Sheng Hsu

发明人： Jong Lee ,  Jer-Shen Maa ,  Douglas Tweet ,  Sheng Hsu

IPC分类号： G01J5/20 ,  H01L21/00 ,  H01L21/20 ,  H01L27/146 ,  H01L29/165 ,  H01L31/028 ,  H01L31/0352 ,  H01L31/10 ,  H01L31/109 ,  H01L31/18

CPC分类号： H01L31/105 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L27/14627 ,  H01L27/14643 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/035281 ,  H01L31/108 ,  H01L31/109 ,  H01L31/1812 ,  Y02E10/547

摘要： A SiGe surface-normal optical path photodetector structure and a method for forming the SiGe optical path normal structure are provided. The method comprises: forming a Si substrate with a surface; forming a Si feature, normal with respect to the Si substrate surface, such as a via, trench, or pillar; depositing SiGe overlying the Si normal feature to a thickness in the range of 5 to 1000 nanometers (nm); and, forming a SiGe optical path normal structure having an optical path length in the range of 0.1 to 10 microns. Typically, the SiGe has a Ge concentration in the range from 5 to 100%. The Ge concentration may be graded to increase with respect to the deposition thickness. For example, the SiGe may have a 20% concentration of Ge at the Si substrate interface, a 30% concentration of Ge at a SiGe film top surface, and a thickness of 400 nm.

摘要翻译： 提供SiGe表面法线光路检测器结构和形成SiGe光路法线结构的方法。 该方法包括：用表面形成Si衬底; 形成Si特征，相对于诸如通孔，沟槽或柱的Si衬底表面是正常的; 将Si覆盖Si正常特征的SiGe沉积到5至1000纳米（nm）范围内的厚度; 并且形成光程长度为0.1〜10微米的SiGe光路法线结构。 通常，SiGe的Ge浓度为5〜100％。 Ge浓度可以相对于沉积厚度而分级增加。 例如，SiGe可以在Si衬底界面处具有20％的Ge浓度，在SiGe膜顶表面上可以具有30％的Ge浓度，并且厚度为400nm。