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    Scan Chain Circuits In Non-Volatile Memory
    1.
    发明申请
    Scan Chain Circuits In Non-Volatile Memory 有权

    公开(公告)号：US20170115342A1

    公开(公告)日：2017-04-27

    申请号：US14919154

    申请日：2015-10-21

    申请人： SanDisk 3D LLC

    发明人： Kesheng Wang

    IPC分类号： G01R31/3177 ,  G01R31/317 ,  G11C16/04

    CPC分类号： G11C16/0483 ,  G01R31/318536 ,  G11C16/08 ,  G11C16/32 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/32 ,  G11C29/50012 ,  G11C2211/5644 ,  G11C2211/5646

    摘要： A bit scan circuit includes N scan blocks corresponding with an N-bit string of binary data. The string is scanned using an input clock signal to count the number of bits having a predetermined binary value. Each scan block includes a single latch to transfer the corresponding bit and to indicate reset. The scan blocks are organized into groups. Each group is enabled by a corresponding token signal. The token signal for each group is asserted after each preceding scan block indicates a pass value. When enabled by its token signal, the first scan block in a group is reset by a first clock signal. A second scan block in the group is enabled for reset after the first scan block indicates the pass value. The second scan block in the group is reset by a second clock signal having pulses that precede corresponding pulses from the first clock signal.

    INDEPENDENT SET/RESET PROGRAMMING SCHEME
    2.
    发明申请
    INDEPENDENT SET/RESET PROGRAMMING SCHEME 有权
    独立设置/复位编程方案

    公开(公告)号：US20160139828A1

    公开(公告)日：2016-05-19

    申请号：US14547473

    申请日：2014-11-19

    申请人： SANDISK 3D LLC

    发明人： Tianhong Yan ,  Tz-yi Liu

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0616 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  Y02D10/154

    摘要： Methods for operating a non-volatile memory that includes a plurality of memory arrays in which each memory array of the plurality of memory arrays may independently perform a SET operation, a RESET operation, or a read operation are described. The ability to independently SET or RESET memory arrays allows a SET operation to be performed on a first set of memory cells within a first memory array at the same time as a RESET operation is performed on a second set of memory cells within a second memory array. In some cases, the first memory array may be associated with a first memory bay and the second memory array may be associated with a second memory bay. Each memory bay may include a memory array, read/write circuits, and control circuitry for determining memory cell groupings and programming memory cells within the memory array based on the memory cell groupings.

    摘要翻译： 描述了包括多个存储器阵列的非易失性存储器的方法，其中多个存储器阵列的每个存储器阵列可以独立地执行SET操作，RESET操作或读取操作。 独立地设置或重置存储器阵列的能力允许在第一存储器阵列内的第一组存储器单元上执行SET操作，同时对第二存储器阵列中的第二组存储器单元执行复位操作 。 在一些情况下，第一存储器阵列可以与第一存储器托架相关联，并且第二存储器阵列可以与第二存储器托架相关联。 每个存储器托架可以包括存储器阵列，读/写电路和用于基于存储器单元分组来确定存储器单元分组和编程存储器阵列内的存储器单元的控制电路。

    Methods and systems to reduce location-based variations in switching characteristics of 3D ReRAM arrays
    4.
    发明授权
    Methods and systems to reduce location-based variations in switching characteristics of 3D ReRAM arrays 有权
    减少3D ReRAM阵列开关特性的基于位置的变化的方法和系统

    公开(公告)号：US09318533B2

    公开(公告)日：2016-04-19

    申请号：US14462374

    申请日：2014-08-18

    申请人： SANDISK 3D LLC

    发明人： Pankaj Kalra ,  Chandrasekhar Gorla ,  Masaaki Higashitani

    IPC分类号： H01L29/06 ,  H01L27/24 ,  H01L45/00 ,  H01L49/02 ,  H01L29/786

    CPC分类号： H01L27/2481 ,  H01L27/2409 ,  H01L28/20 ,  H01L29/78642 ,  H01L31/0547 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  Y02E10/52

    摘要： Methods for reducing location-based variations in the switching characteristics of memory cells within a memory array are described. In some cases, the resistance of an embedded resistor within each memory cell may be set to reduce the overall variation in series resistances for the memory cells within a memory array. For example, embedded resistors associated with far-far bits may be set to a lower resistance than embedded resistors associated with near-near bits. An embedded resistor may comprise a layer of polysilicon within a memory cell. Selective ion implantation may be used to reduce the embedded resistor resistance for memory cells within a particular region of the memory array and to form two or more different sets of embedded resistors within the memory array.

    摘要翻译： 描述了用于减少存储器阵列内的存储器单元的开关特性的基于位置的变化的方法。 在一些情况下，可以设置每个存储单元内的嵌入式电阻器的电阻以减小存储器阵列内的存储单元的串联电阻的总体变化。 例如，与远近位相关联的嵌入式电阻器可以被设置为比与近近位相关联的嵌入式电阻器更低的电阻。 嵌入式电阻器可以包括存储器单元内的多晶硅层。 可以使用选择性离子注入来降低存储器阵列的特定区域内的存储器单元的嵌入式电阻器电阻并且在存储器阵列内形成两个或更多个不同的嵌入式电阻器组。

    Non-volatile memory having 3D array architecture with bit line voltage control and methods thereof
    6.
    发明授权
    Non-volatile memory having 3D array architecture with bit line voltage control and methods thereof 有权
    具有具有位线电压控制的3D阵列架构的非易失性存储器及其方法

    公开(公告)号：US09281029B2

    公开(公告)日：2016-03-08

    申请号：US13794344

    申请日：2013-03-11

    申请人： SanDisk 3D LLC

    发明人： Raul Adrian Cernea

    IPC分类号： G11C7/12 ,  G11C8/08 ,  G11C11/4094 ,  G11C5/02 ,  G11C7/18 ,  G11C13/00

    CPC分类号： G11C7/12 ,  G11C5/025 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4094 ,  G11C13/0021 ,  G11C13/004

    摘要： In a 3D memory with vertical local bit lines, each local bit line is switchably connected to a node on a global bit line having first and second ends, the local bit line voltage is maintained at a predetermined reference level in spite of being driven by a bit line driver from a first end of the global bit line that constitutes variable circuit path length and circuit serial resistance. This is accomplished by a feedback voltage regulator comprising a voltage clamp at the first end of the global bit line controlled by a bit line voltage comparator at the second end of the global bit line. The comparator compares the bit line voltage sensed from the second end with the predetermined reference level and outputs a control voltage to control the voltage clamp In this way the voltage at the local bit line is regulated at the reference voltage.

    摘要翻译： 在具有垂直局部位线的3D存储器中，每个局部位线可切换地连接到具有第一和第二端的全局位线上的节点，局部位线电压被维持在预定的参考电平，尽管由 全局位线第一端的位线驱动器构成可变电路路径长度和电路串联电阻。 这是通过一个反馈电压调节器实现的，该电压调节器包括在由全局位线的第二端的位线电压比较器控制的全局位线的第一端的电压钳位。 比较器将从第二端检测的位线电压与预定参考电平进行比较，并输出控制电压以控制电压钳位。以这种方式，局部位线处的电压被调节在参考电压。

    ReRAM cells with diffusion-resistant metal silicon oxide layers
    7.
    发明授权
    ReRAM cells with diffusion-resistant metal silicon oxide layers 有权
    ReRAM电池具有耐扩散性的金属氧化硅层

    公开(公告)号：US09246091B1

    公开(公告)日：2016-01-26

    申请号：US14338979

    申请日：2014-07-23

    申请人： Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    发明人： Yun Wang ,  Federico Nardi

    IPC分类号： H01L27/24 ,  H01L45/00

    CPC分类号： H01L45/1253 ,  H01L27/24 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616

    摘要： A metal silicon oxide barrier layer between a nitride electrode containing the same metal and an oxide variable-resistance layer in a ReRAM cell prevents the metal from diffusing into the variable-resistance layer and prevents oxygen from diffusing into and oxidizing the electrode. Compound oxides of the same metal and silicon with varying stoichiometries and metal/silicon ratios may optionally replace part or all of the variable-resistance layer, a defect-reservoir layer, or both. The metal nitride electrode may include a metal silicon nitride current-limiting portion. Optionally, all the layers sharing the common metal may be formed in-situ as part of a single unit process, such as atomic layer deposition.

    摘要翻译： 在ReRAM单元中含有相同金属的氮化物电极和氧化物可变电阻层之间的金属氧化硅阻挡层防止金属扩散到可变电阻层中，并防止氧气扩散到氧化电极。 具有不同化学计量和金属/硅比的相同金属和硅的复合氧化物可任选地替代部分或全部可变电阻层，缺陷储层或两者。 金属氮化物电极可以包括金属氮化硅限流部。 可选地，共享公共金属的所有层可以原位形成为单个单元工艺的一部分，例如原子层沉积。