公开(公告)号：US20200075561A1

公开(公告)日：2020-03-05

申请号：US16298421

申请日：2019-03-11

申请人： JI HWANG KIM ,  JONGBO SHIM ,  WON IL LEE ,  JANGWOO LEE ,  YOUNG KUN JEE

发明人： JI HWANG KIM ,  JONGBO SHIM ,  WON IL LEE ,  JANGWOO LEE ,  YOUNG KUN JEE

IPC分类号： H01L25/10 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538

摘要： A semiconductor package includes a first substrate, a first semiconductor chip mounted on the first substrate, an interposer substrate and a chip package stacked on the first semiconductor chip, and a first molding layer encapsulating the first semiconductor chip and the chip package. The chip package includes a second semiconductor chip on the interposer substrate. The interposer substrate has a base layer consisting of silicon, a conductive pattern on a top surface of the base layer, and a through-electrode extending through the base layer and connected to the conductive pattern.

公开(公告)号：US20120315726A1

公开(公告)日：2012-12-13

申请号：US13491055

申请日：2012-06-07

申请人： HAK-KYOON BYUN ,  Bu-Won Kim ,  Raehyung Do ,  JongBo Shim ,  Woodong Lee

发明人： HAK-KYOON BYUN ,  Bu-Won Kim ,  Raehyung Do ,  JongBo Shim ,  Woodong Lee

IPC分类号： H01L21/82

CPC分类号： H01L21/784 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/3178 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/80 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/03009 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/03903 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05558 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0566 ,  H01L2224/06135 ,  H01L2224/08145 ,  H01L2224/08148 ,  H01L2224/08155 ,  H01L2224/27009 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/80815 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2924/01028 ,  H01L2224/27 ,  H01L2924/00 ,  H01L2224/05552

摘要： Provided are methods of manufacturing a semiconductor chip package. The method includes forming a plurality of semiconductor chips, each of which includes a semiconductor substrate having a front and back surfaces facing each other, a chip pad provided on the front surface of the semiconductor substrate, and an interconnection pattern extending from the chip pad along a sidewall of the semiconductor substrate, stacking the semiconductor chips such that the interconnection patterns of the semiconductor chips directly contact each other, and reflowing the interconnection patterns of the semiconductor chips to connect the stacked semiconductor chips with each other.

摘要翻译： 提供制造半导体芯片封装的方法。 该方法包括形成多个半导体芯片，每个半导体芯片包括具有彼此面对的正面和背面的半导体衬底，设置在半导体衬底的前表面上的芯片焊盘以及从芯片焊盘延伸的互连图案 半导体衬底的侧壁，堆叠半导体芯片，使得半导体芯片的互连图案直接相互接触，并且回流半导体芯片的互连图案以将堆叠的半导体芯片彼此连接。

公开(公告)号：US20160148888A1

公开(公告)日：2016-05-26

申请号：US14948228

申请日：2015-11-20

申请人： Seung-Kwan RYU ,  Jongbo SHIM ,  Eunchul AHN ,  Taeje CHO

发明人： Seung-Kwan RYU ,  Jongbo SHIM ,  Eunchul AHN ,  Taeje CHO

IPC分类号： H01L23/00 ,  H01L23/48

CPC分类号： H01L24/14 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/06517 ,  H01L2224/09519 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13012 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14051 ,  H01L2224/14104 ,  H01L2224/16238 ,  H01L2224/17517 ,  H01L2224/17519 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81444 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

摘要： A semiconductor device may include a semiconductor substrate, a conductive pad on the semiconductor substrate, a passivation layer overlying the semiconductor substrate and exposing the conductive pad, and a bump structure. The bump structure may include a first bump structure on the conductive pad and a second bump structure on the passivation layer. The first bump structure may include a base bump layer, a first pillar bump layer, and a first solder bump layer that are sequentially stacked on the conductive pad. The second bump structure may include a second pillar bump layer and a second solder bump layer that are sequentially stacked on the passivation layer.

摘要翻译： 半导体器件可以包括半导体衬底，半导体衬底上的导电焊盘，覆盖半导体衬底并暴露导电焊盘的钝化层和凸块结构。 凸块结构可以包括导电焊盘上的第一凸起结构和钝化层上的第二凸起结构。 第一凸块结构可以包括顺序地堆叠在导电焊盘上的基底凸起层，第一柱凸起层和第一焊料凸块层。 第二凸起结构可以包括顺序地堆叠在钝化层上的第二柱状凸起层和第二焊料凸块层。

公开(公告)号：US20140117506A1

公开(公告)日：2014-05-01

申请号：US13974254

申请日：2013-08-23

申请人： JiSun HONG ,  Hyunki KIM ,  JongBo SHIM ,  SeokWon LEE ,  Kyoungsei CHOI

发明人： JiSun HONG ,  Hyunki KIM ,  JongBo SHIM ,  SeokWon LEE ,  Kyoungsei CHOI

IPC分类号： H01L23/31

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00

摘要： A semiconductor device includes a first semiconductor package including a first mold part, a second semiconductor package including a second mold part, a connecting pattern configured to electrically connect the first and second semiconductor packages to each other, and a molding pattern between the first and second semiconductor packages. The molding pattern extends to cover at least a portion of a sidewall of only the second semiconductor package.

摘要翻译： 一种半导体器件包括：第一半导体封装，包括第一模具部件，包括第二模具部件的第二半导体封装，被配置为使第一和第二半导体封装彼此电连接的连接图案;以及第一和第二半导体封装之间的模制图案 半导体封装。 模制图案延伸以覆盖仅第二半导体封装的侧壁的至少一部分。