公开(公告)号：US20240164064A1

公开(公告)日：2024-05-16

申请号：US18231179

申请日：2023-08-07

申请人： Peter C. SALMON

发明人： Peter C. SALMON

IPC分类号： H05K7/20 ,  G06F1/26 ,  H05K5/06

CPC分类号： H05K7/20772 ,  G06F1/26 ,  H05K5/065 ,  H05K7/20236

摘要： A zettascale supercomputer may be configured using an array of servers organized in computer pods comprising 4-60 servers per pod. Each server includes computer modules immersed in a tank in which cooling water is flowing. Copper bus bars deliver power to each pod in a range of 4-180 MW. Cooling water is delivered to each pod in a range of 200-24,000 gallons per minute. Supercomputers having an operating power in a range of 4 MW-10 GW are described.

公开(公告)号：US10689754B2

公开(公告)日：2020-06-23

申请号：US16387144

申请日：2019-04-17

申请人： Peter C. Salmon

发明人： Peter C. Salmon

IPC分类号： C23C16/04 ,  G11C11/24 ,  H01L27/01 ,  H01L21/70 ,  H01L27/12 ,  H01L21/3213 ,  H01L21/02 ,  B41M1/12 ,  G03G13/02 ,  G03G15/02

摘要： A charge storage cell includes a substrate having a back side conductive layer or conductive element, a top side metal pad coupled to the substrate, and an insulating layer formed on the metal pad. The metal pad will support an electric charge injected through the insulating layer by a charged particle beam. A regular array of charge storage cells provides a charge storage array.

公开(公告)号：US20190252017A1

公开(公告)日：2019-08-15

申请号：US16387144

申请日：2019-04-17

申请人： Peter C. Salmon

发明人： Peter C. Salmon

IPC分类号： G11C11/24 ,  H01L27/01 ,  H01L21/70

摘要： A charge storage cell includes a substrate having a back side conductive layer or conductive element, a top side metal pad coupled to the substrate, and an insulating layer formed on the metal pad. The metal pad will support an electric charge injected through the insulating layer by a charged particle beam. A regular array of charge storage cells provides a charge storage array.

公开(公告)号：US10312319B2

公开(公告)日：2019-06-04

申请号：US15695697

申请日：2017-09-05

申请人： Peter C. Salmon

发明人： Peter C. Salmon

IPC分类号： H01L21/00 ,  H01L49/02 ,  G11C11/24 ,  H01L27/01 ,  H01L21/70 ,  H01L27/12

摘要： A charge storage cell includes a conductive substrate, a substantially vertical post comprising a first insulating material coupled to the conductive substrate and a conductive cap coupled to the vertical post. The charge storage cell also includes a top side planarizing layer comprising a second insulating material and covering the conductive cap. The conductive cap will support an electric charge injected through the top side planarizing layer by a modulated charged particle beam.

公开(公告)号：US09227220B1

公开(公告)日：2016-01-05

申请号：US13684266

申请日：2012-11-23

申请人： Peter C. Salmon

发明人： Peter C. Salmon

IPC分类号： B05D1/36 ,  B05D3/14

CPC分类号： G03G15/224

摘要： A patterning method involves providing a flexible web comprising embedded electrical charges, deposition material having polar properties, a substrate, and a transfer electrode, wherein the flexible web is passed through the deposition material and accumulates material in accordance with the embedded electrical charges, and the accumulated material is transferred to the substrate at the transfer electrode. A production line may be configured in a reel-to-reel implementation. Each station may include finishing operations on the deposited material, including but not limited to heating, annealing, curing, fusing, surface-treating, laser-processing, charge neutralizing, barrier processing, etching, electroplating, and passivating.

摘要翻译： 图案化方法包括提供包括嵌入电荷的柔性网，具有极性的沉积材料，基底和转移电极，其中柔性网通过沉积材料并根据嵌入的电荷累积材料， 堆积的材料被转移到转移电极处的衬底。 生产线可以以卷到盘的方式配置。 包括但不限于加热，退火，固化，定影，表面处理，激光加工，电荷中和，屏障处理，蚀刻，电镀和钝化，每个工位可以包括对沉积材料的精加工操作。

公开(公告)号：US07586747B2

公开(公告)日：2009-09-08

申请号：US11495954

申请日：2006-07-27

申请人： Peter C. Salmon

发明人： Peter C. Salmon

IPC分类号： H05K7/20

CPC分类号： G02B6/43 ,  H01L23/142 ,  H01L23/3171 ,  H01L23/467 ,  H01L23/473 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/10 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1627 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  Y10T29/49128 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for building scalable electronic subsystems is described. Stackable modules employ copper substrates with solder connections between modules, and a ball grid array interface is provided at the bottom of the stack. A cooling channel is optionally provided between each pair of modules. Each module is re-workable because all integrated circuit attachments within the module employ re-workable flip chip connectors. Also, defective modules can be removed from the stack by directing hot inert gas at externally accessible solder connections.

摘要翻译： 描述了用于构建可伸缩电子子系统的方法。 可堆叠模块采用铜基板，在模块之间具有焊接连接，并且在堆叠底部提供球栅阵列接口。 可选地，在每对模块之间设置冷却通道。 每个模块都可重新使用，因为模块内的所有集成电路附件均采用可重复使用的倒装芯片连接器。 此外，通过将热惰性气体引导到外部可访问的焊接连接处，可以将有缺陷的模块从堆叠中移除。

公开(公告)号：US20090192753A1

公开(公告)日：2009-07-30

申请号：US12401357

申请日：2009-03-10

申请人： Peter C. Salmon

发明人： Peter C. Salmon

IPC分类号： G06F19/00 ,  G01R31/00 ,  G06F15/18

CPC分类号： G01R31/31727 ,  G01R31/31724 ,  G01R31/3187

摘要： The technology and economics of system testing have evolved to the point where a radical change in methodology is needed for effective functional testing of systems at clock rates of 1 GHz and higher. Rather than providing a test fixture to interface between the system under test and an external tester, it is preferable to provide critical testing functions within each electronic system in the form of one or more special-purpose test chips. An architecture is proposed that supports full-speed testing with improved noise margins, and also efficient methods for learning correct system behavior and generating the test vectors. The test program is preferably written using the same programming language as used for the system application.

摘要翻译： 系统测试的技术和经济已经发展到了在1 GHz及更高​​的时钟速率下对系统进行有效功能测试所需的方法论的根本改变。 优选的是，在一个或多个专用测试芯片的形式下，在每个电子系统内提供关键的测试功能。 提出了一种架构，支持全速测试，提高噪声容限，以及学习正确系统行为和生成测试向量的有效方法。 测试程序优选使用与系统应用程序相同的编程语言编写。

公开(公告)号：US07427809B2

公开(公告)日：2008-09-23

申请号：US11015213

申请日：2004-12-16

申请人： Peter C. Salmon

发明人： Peter C. Salmon

IPC分类号： H01L29/40 ,  H01L23/34

CPC分类号： H01L23/49827 ,  H01L21/4853 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/36 ,  H01L23/49811 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11332 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/11554 ,  H01L2224/11901 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/16237 ,  H01L2224/81052 ,  H01L2224/81101 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06517 ,  H01L2225/06575 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/3651 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05099

摘要： A tightly packed three-dimensional electronic system or subsystem comprising multiple stacks of semiconductor elements is described. The system is repairable because the elements connect together using re-workable flip chip connectors; each flip chip connector comprises a conductive spring element on one side and a corresponding well filled with solder on the other side. The spring elements relieve stresses at the interfaces and allow the component stacks to remain flat; they also provide vertical compliance for easing assembly of elements that have been imperfectly thinned or planarized. Semiconductor integration platforms may be used to integrate active and passive devices, multi-layer interconnections, through wafer connections, I/O plugs, and terminals for attachment of other semiconductor elements or cables.

摘要翻译： 描述了包括多个半导体元件堆叠的紧密包装的三维电子系统或子系统。 该系统是可修复的，因为元件使用可重复使用的倒装芯片连接器连接在一起; 每个倒装芯片连接器包括在一侧上的导电弹簧元件和在另一侧上填充有焊料的对应的阱。 弹簧元件减轻了界面处的应力，并允许组件堆叠保持平坦; 它们还提供了垂直顺应性，以减少已经不完全变薄或平坦化的元件的组装。 半导体集成平台可用于通过晶片连接，I / O插头和端子来集成有源和无源器件，多层互连，以连接其他半导体元件或电缆。

公开(公告)号：US07408258B2

公开(公告)日：2008-08-05

申请号：US10783662

申请日：2004-02-20

申请人： Peter C. Salmon

发明人： Peter C. Salmon

IPC分类号： H01L23/04

CPC分类号： H01L21/486 ,  H01L2224/16 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/005 ,  H05K3/107 ,  H05K3/388 ,  H05K3/423 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/465 ,  H05K2201/0141 ,  H05K2201/09563 ,  H05K2203/0108 ,  H01L2924/00

摘要： A method for fabricating copper-faced electronic modules is described. These modules are mechanically robust, thermally accessible for cooling purposes, and capable of supporting high power circuits, including operation at 10 GHz and above. An imprinting method is described for patterning the copper layers of the interconnection circuit, including a variation of the imprinting method to create a special assembly layer having wells filled with solder. The flip chip assembly method comprising stud bumps inserted into wells enables unlimited rework of defective chips. The methods can be applied to multi chip modules that may be connected to other electronic systems or subsystems using feeds through the copper substrate, using a new type of module access cable, or by wireless means. The top copper plate can be replaced with a chamber containing circulating cooling fluid for aggressive cooling that may be required for servers and supercomputers. Application of these methods to create a liquid cooled supercomputer is described.

摘要翻译： 对铜面电子模块的制造方法进行说明。 这些模块具有机械坚固耐用性，可以进行冷却，可用于支持高功率电路，包括在10 GHz及以上的工作。 描述了用于图案化互连电路的铜层的压印方法，包括压印方法的变化以产生具有填充有焊料的阱的特殊组装层。 包括插入孔中的螺柱凸块的倒装芯片组装方法能够对有缺陷的芯片进行无限的返修。 该方法可以应用于可以使用新型的模块接入电缆或通过无线装置连接到使用通过铜基板的馈送的其他电子系统或子系统的多芯片模块。 顶部的铜板可以被包含循环冷却流体的腔室所替代，用于服务器和超级计算机所需的积极冷却。 描述了这些方法的应用以创建液冷式超级计算机。

公开(公告)号：US06927471B2

公开(公告)日：2005-08-09

申请号：US10237640

申请日：2002-09-06

申请人： Peter C. Salmon

发明人： Peter C. Salmon

IPC分类号： H01L23/498 ,  H01L23/538 ,  H05K1/00 ,  H05K1/11 ,  H05K3/00 ,  H05K3/34 ,  H05K3/46 ,  H01L29/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L24/16 ,  H01L23/49811 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/25 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0289 ,  H05K1/115 ,  H05K3/007 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/4682 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0568 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/20751 ,  H01L2924/00

摘要： This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths of 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is used to fabricate the interconnection circuits. A polymer base layer is formed on a glass carrier with an intermediate release layer. Alternate layers of metal and dielectric are formed on the base layer, and patterned to create an array of multi-layer interconnection circuits on the glass panel. A thick layer of polymer is deposited on the interconnection circuit, and openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings to form wells filled with solder. After dicing the glass carrier to form separated interconnection circuits, IC chips are stud bumped and assembled using flip chip bonding, wherein the stud bumps on the components are inserted into corresponding wells on the interconnection circuits. The IC chips are tested and reworked to form tested circuit assemblies. Methods for connecting to testers and to other modules and electronic systems are described. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server embodiment is also described.

摘要翻译： 本说明书描述了用于制造电子系统模块的技术。 该模块包括轨迹宽度为5微米或更小的柔性多层互连电路。 用于制造液晶显示器，LCD，面板的玻璃面板制造设备用于制造互连电路。 在具有中间剥离层的玻璃载体上形成聚合物基层。 金属和电介质的交替层形成在基底层上，并被图案化以在玻璃面板上产生多层互连电路阵列。 在互连电路上沉积一层聚合物，并在输入/输出（I / O）焊盘位置形成开口。 将焊膏沉积在开口中以形成填充有焊料的孔。 在切割玻璃载体以形成分离的互连电路之后，使用倒装芯片接合对IC芯片进行螺柱凸起并组装，其中部件上的螺柱凸起插入到互连电路上的对应的孔中。 对IC芯片进行测试和返工以形成测试电路组件。 描述了连接到测试仪和其他模块和电子系统的方法。 提供模块封装层用于密封和电磁屏蔽。 还描述了刀片服务器实施例。