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    THERMALLY ISOLATED ELECTRONICS UTILITIES CAVITY FOR A SUBSTRATE CARRIER
    1.
    发明申请
    THERMALLY ISOLATED ELECTRONICS UTILITIES CAVITY FOR A SUBSTRATE CARRIER 审中-公开

    公开(公告)号：US20190355607A1

    公开(公告)日：2019-11-21

    申请号：US15986452

    申请日：2018-05-22

    申请人： Applied Materials, Inc.

    发明人： Shreesha Y. RAO ,  Joseph VINCENT ,  Wenwei QIAO ,  John M. WHITE

    IPC分类号： H01L21/683 ,  H01L21/67 ,  H01M2/10

    摘要： Described herein is a substrate carrier comprises a plurality of electrostatic chuck panels and a carrier body. The plurality of electrostatic chuck panels is disposed on the carrier body. The carrier body has an electronics utilities cavity, and a thermal insulating material disposed on at least one wall of the electronics utilities cavity. A battery is disposed within the electronics cavity, and is configured to provide a first power supply signal to control electronics. The carrier body may additionally include a first body member having the electrostatic chuck panels disposed thereon, and a second body member separated from the first body member by thermal breaks. The electronics utilities cavity may be housed within the second body member of the carrier body.

    PLASMA UNIFORMITY CONTROL BY GAS DIFFUSER HOLE DESIGN
    4.
    发明申请
    PLASMA UNIFORMITY CONTROL BY GAS DIFFUSER HOLE DESIGN 审中-公开
    气体扩散器孔设计的等离子体均匀性控制

    公开(公告)号：US20160056019A1

    公开(公告)日：2016-02-25

    申请号：US14932618

    申请日：2015-11-04

    申请人： Applied Materials, Inc.

    发明人： Soo Young CHOI ,  John M. WHITE ,  Qunhua WANG ,  Li Hou ,  Ki Woon KIM ,  Shinichi KURITA ,  Tae Kyung WON ,  Suhail ANWAR ,  Beom Soo Park ,  Robin L. TINER

    IPC分类号： H01J37/32

    CPC分类号： H01J37/3244 ,  C23C16/345 ,  C23C16/455 ,  C23C16/45565 ,  C23C16/5096 ,  H01J37/32082 ,  H01J37/32091 ,  H01J37/32541 ,  H01J37/32596 ,  H01J2237/327 ,  H01J2237/3321 ,  H01J2237/3323 ,  H01J2237/3325 ,  Y10T29/49885 ,  Y10T29/49996

    摘要： Embodiments of a gas diffuser plate for distributing gas in a processing chamber are provided. The gas distribution plate includes a diffuser plate having an upstream side and a downstream side, and a plurality of gas passages passing between the upstream and downstream sides of the diffuser plate. The gas passages include hollow cathode cavities at the downstream side to enhance plasma ionization. The depths, the diameters, the surface area and density of hollow cathode cavities of the gas passages that extend to the downstream end can be gradually increased from the center to the edge of the diffuser plate to improve the film thickness and property uniformity across the substrate. The increasing diameters, depths and surface areas from the center to the edge of the diffuser plate can be created by bending the diffuser plate toward downstream side, followed by machining out the convex downstream side. Bending the diffuser plate can be accomplished by a thermal process or a vacuum process. The increasing diameters, depths and surface areas from the center to the edge of the diffuser plate can also be created computer numerically controlled machining. Diffuser plates with gradually increasing diameters, depths and surface areas of the hollow cathode cavities from the center to the edge of the diffuser plate have been shown to produce improved uniformities of film thickness and film properties.

    摘要翻译： 提供了用于在处理室中分配气体的气体扩散板的实施例。 气体分配板包括具有上游侧和下游侧的扩散板，以及在扩散板的上游侧和下游侧之间通过的多个气体通路。 气体通道包括在下游侧的中空阴极腔，以增强等离子体电离。 延伸到下游端的气体通道的空心阴极腔的深度，直径，表面积和密度可以从扩散板的中心到边缘逐渐增加，以改善衬底上的膜厚度和性能均匀性 。 从扩散板的中心到边缘的直径，深度和表面积的增加可以通过向下游侧弯曲扩散板，然后在凸出的下游侧加工出来。 扩散板的弯曲可以通过热处理或真空工艺来实现。 从扩散板的中心到边缘的直径，深度和表面积的增加也可以用计算机数字控制加工。 具有从扩散板的中心到边缘的中空阴极腔的直径逐渐增加，深度和表面积逐渐增大的扩散板已被证明可以产生改善的膜厚度和膜性质的均匀性。

    FULL-AREA COUNTER-FLOW HEAT EXCHANGE SUBSTRATE SUPPORT
    7.
    发明申请
    FULL-AREA COUNTER-FLOW HEAT EXCHANGE SUBSTRATE SUPPORT 审中-公开

    公开(公告)号：US20170321323A1

    公开(公告)日：2017-11-09

    申请号：US15149063

    申请日：2016-05-06

    申请人： Applied Materials, Inc.

    发明人： John M. WHITE

    IPC分类号： C23C16/458 ,  H01J37/32 ,  F28D15/00 ,  F28F9/02

    CPC分类号： C23C16/4586 ,  C23C16/46 ,  C23C16/505 ,  F28D15/00 ,  F28F9/026 ,  F28F2250/10 ,  H01J37/32715 ,  H01J37/32724 ,  H01J2237/3321 ,  H01L51/00

    摘要： Embodiments described herein generally relate to a temperature control system in a substrate support assembly. In one embodiment, a substrate support assembly is disclosed. The substrate support assembly includes a support plate assembly The support plate assembly includes a first fluid supply manifold, a second fluid supply manifold, a first fluid return manifold, a second fluid return manifold, a plurality of first fluid passages, a plurality of second fluid passages, and a fluid supply conduit. The plurality of first fluid passages extend from the first fluid supply manifold to the first fluid return manifold. The plurality of second fluid passages extend from the second fluid supply manifold to the second fluid return manifold. The plurality of fluid passages extend across an upper surface of the support plate assembly in an alternating manner. The fluid supply conduit is configured to supply a fluid to the fluid supply manifolds.

    MULTILAYER PASSIVATION OR ETCH STOP TFT
    9.
    发明申请
    MULTILAYER PASSIVATION OR ETCH STOP TFT 有权
    多层钝化或蚀刻停止TFT

    公开(公告)号：US20160013320A1

    公开(公告)日：2016-01-14

    申请号：US14773209

    申请日：2014-03-04

    申请人： APPLIED MATERIALS INC.

    发明人： Dong-kil YIM ,  Tae Kyung WON ,  Seon-Mee CHO ,  John M. WHITE

    IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/24

    CPC分类号： H01L29/66969 ,  H01L21/467 ,  H01L29/24 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/7869

    摘要： The present invention generally relates to TFTs and methods for fabricating TFTs. For either back channel etch TFTs or for etch stop TFTs, multiple layers for the passivation layer or the etch stop layers permits a very dense capping layer to be formed over a less dense back channel protection layer. The capping layer can be sufficiently dense so that few pin holes are present and thus, hydrogen may not pass through to the semiconductor layer. As such, hydrogen containing precursors may be used for the capping layer deposition.

    摘要翻译： 本发明一般涉及TFT和TFT的制造方法。 对于背沟道蚀刻TFT或蚀刻停止TFT，用于钝化层或蚀刻停止层的多个层允许在较不致密的背沟道保护层上形成非常密集的覆盖层。 封盖层可以是足够密实的，从而存在很少的针孔，因此氢不能通过半导体层。 因此，含氢前体可以用于覆盖层沉积。

    BUFFER LAYERS FOR METAL OXIDE SEMICONDUCTORS FOR TFT
    10.
    发明申请
    BUFFER LAYERS FOR METAL OXIDE SEMICONDUCTORS FOR TFT 有权
    用于TFT的金属氧化物半导体的缓冲层

    公开(公告)号：US20140264354A1

    公开(公告)日：2014-09-18

    申请号：US14203433

    申请日：2014-03-10

    申请人： APPLIED MATERIALS, INC.

    发明人： Kurtis LESCHKIES ,  Steven VERHAVERBEKE ,  Robert VISSER ,  John M. WHITE ,  Yan YE ,  Dong-Kil YIM

    IPC分类号： H01L29/786

    CPC分类号： H01L29/7869 ,  H01L29/4908

    摘要： The present invention generally relates to a thin film semiconductor device having a buffer layer formed between the semiconductor layer and one or more layers. In one embodiment, a thin film semiconductor device includes a semiconductor layer having a first work function and a first electron affinity level, a buffer layer having a second work function greater than the first work function and a second electron affinity level that is less than the first electron affinity level; and a gate dielectric layer having a third work function less than the second work function and a third electron affinity level that is greater than the second electron affinity level.

    摘要翻译： 本发明一般涉及一种在半导体层与一层或多层之间形成缓冲层的薄膜半导体器件。 在一个实施例中，薄膜半导体器件包括具有第一功函数和第一电子亲和度的半导体层，具有大于第一功函数的第二功函数的缓冲层和小于第一功函数的第二电子亲和度 第一电子亲和力水平; 以及具有小于第二功函数的第三功函数和大于第二电子亲和度的第三电子亲和度的栅介质层。