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46 条记录 (耗时 0.021 秒)

    Thermal dispensing enhancement for high performance flip chip BGA (HPFCBGA)
    1.
    发明授权
    Thermal dispensing enhancement for high performance flip chip BGA (HPFCBGA) 有权
    高性能倒装芯片BGA（HPFCBGA）的散热增强

    公开(公告)号：US07026711B2

    公开(公告)日：2006-04-11

    申请号：US10737496

    申请日：2003-12-16

    申请人： Daniel Lee ,  Chender Huang ,  Chien-Hsiun Lee

    发明人： Daniel Lee ,  Chender Huang ,  Chien-Hsiun Lee

    IPC分类号： H01L23/10 ,  H01L23/12 ,  H01L23/48 ,  H01L23/52

    CPC分类号： H01L23/36 ,  H01L23/3735 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/16195

    摘要： A microelectronic package comprising a device substrate having first and second opposing surfaces and comprising a plurality of microelectronic devices. The microelectronic package also includes a plurality of electrically conductive members coupled to corresponding ones of the plurality of microelectronics device and extending away from the first surface. A thermally conductive layer is located on the second surface of the device substrate, and a package substrate is coupled to the device substrate, the package substrate having a plurality of electrically conductive traces coupled to corresponding ones of the plurality of electrically conductive members.

    摘要翻译： 一种微电子封装，其包括具有第一和第二相对表面并且包括多个微电子器件的器件衬底。 微电子封装还包括耦合到多个微电子器件中的相应微电子器件并且远离第一表面延伸的多个导电构件。 导热层位于器件衬底的第二表面上，并且封装衬底耦合到器件衬底，封装衬底具有耦合到多个导电构件中的相应导电构件的多个导电迹线。

    Thermal dispensing enhancement for high performance flip chip BGA (HPFCBGA)
    2.
    发明申请
    Thermal dispensing enhancement for high performance flip chip BGA (HPFCBGA) 有权
    高性能倒装芯片BGA（HPFCBGA）的散热增强

    公开(公告)号：US20050127502A1

    公开(公告)日：2005-06-16

    申请号：US10737496

    申请日：2003-12-16

    申请人： Daniel Lee ,  Chender Huang ,  C. H. Lee

    发明人： Daniel Lee ,  Chender Huang ,  C. H. Lee

    IPC分类号： H01L23/34 ,  H01L23/36 ,  H01L23/373

    CPC分类号： H01L23/36 ,  H01L23/3735 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/16195

    摘要： A microelectronic package comprising a device substrate having first and second opposing surfaces and comprising a plurality of microelectronic devices. The microelectronic package also includes a plurality of electrically conductive members coupled to corresponding ones of the plurality of microelectronics device and extending away from the first surface. A thermally conductive layer is located on the second surface of the device substrate, and a package substrate is coupled to the device substrate, the package substrate having a plurality of electrically conductive traces coupled to corresponding ones of the plurality of electrically conductive members.

    摘要翻译： 一种微电子封装，其包括具有第一和第二相对表面并且包括多个微电子器件的器件衬底。 微电子封装还包括耦合到多个微电子器件中的相应微电子器件并且远离第一表面延伸的多个导电构件。 导热层位于器件衬底的第二表面上，并且封装衬底耦合到器件衬底，封装衬底具有耦合到多个导电构件中的相应导电构件的多个导电迹线。

    Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling
    8.
    发明授权
    Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling 有权
    用于制造具有减少的分层和剥离的半导体晶片的装置和方法

    公开(公告)号：US07294937B2

    公开(公告)日：2007-11-13

    申请号：US11495057

    申请日：2006-07-28

    申请人： Chao-Yuan Su ,  Pei-Haw Tsao ,  Hsin-Hui Lee ,  Chender Huang ,  Shang Y. Hou ,  Shin Puu Jeng ,  Hao-Yi Tsai ,  Chenming Hu

    发明人： Chao-Yuan Su ,  Pei-Haw Tsao ,  Hsin-Hui Lee ,  Chender Huang ,  Shang Y. Hou ,  Shin Puu Jeng ,  Hao-Yi Tsai ,  Chenming Hu

    IPC分类号： H01L23/544

    CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A1 is defined on the first scribe line and is defined by the equation A1=D1×S1, where D1 is the distance from the corner point of the die toward the main area of the die, and S1 is the width of the first scribe line. Free area AS is defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation AS=S1×S2, where S2 is the width of the second scribe line.

    摘要翻译： 具有限制测试键放置的自由区域的多层半导体结构。 第一和第二划线相交以定义模具的一个角点。 第一和第二划痕线是多层结构的一部分，多层结构的至少一层是低k电介质层。 自由区域A 1 <1>在第一划线上被定义并且由等式1定义1 D 1 1 ，其中D <1> 是从模具的角点到模具的主要区域的距离，S 1是第一划线的宽度。 在第一划线和与模具相邻的第二划线之间的交叉点处限定自由区域A＆S，并且由公式A S S = 其中S 2 <2>是第二划线的宽度。

    Three dimensional package type stacking for thinner package application
    10.
    发明申请
    Three dimensional package type stacking for thinner package application 审中-公开
    三维包装类型堆叠为更薄的包装应用

    公开(公告)号：US20060073635A1

    公开(公告)日：2006-04-06

    申请号：US10951428

    申请日：2004-09-28

    申请人： Chao-Yuan Su ,  Pei-Haw Tsao ,  Chender Huang

    发明人： Chao-Yuan Su ,  Pei-Haw Tsao ,  Chender Huang

    IPC分类号： H01L21/50

    CPC分类号： H01L25/50 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A stacked semiconductor device, and method of making, having a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a first substrate. Solder balls are connected to contacts on the upper surface of the first substrate and a non-conductive layer is provided overlaying the first substrate and the first semiconductor chip. The solder balls are secured in cavities formed in the layer and extend beyond the top surface of the layer. A second semiconductor chip mounted on a second substrate is stacked on the layer with contacts on the lower surface of the second substrate in electrical contact with the extended portion of the solder balls, thereby connecting the second semiconductor chip with the first semiconductor chip.

    摘要翻译： 具有堆叠成一个封装的所需尺寸的多个半导体芯片的叠层半导体器件和制造方法安装在第一衬底上。 焊球与第一基板的上表面上的触点连接，并且设置覆盖第一基板和第一半导体芯片的非导电层。 焊球被固定在形成在层中的空腔中并且延伸超出该层的顶表面。 安装在第二基板上的第二半导体芯片在第二基板的下表面上的触点层叠在与焊球的延伸部分电接触的层上，从而将第二半导体芯片与第一半导体芯片连接。