公开(公告)号：US5028983A

公开(公告)日：1991-07-02

申请号：US263835

申请日：1988-10-27

申请人： Harry R. Bickford ,  Mark F. Bregman ,  Thomas M. Cipolla ,  John Gow, III ,  Peter G. Ledermann ,  Ekkehard F. Miersch ,  Leonard T. Olson ,  David P. Pagnani ,  Timothy C. Reiley ,  Uh-Po E. Tsou ,  Walter V. Vilkelis

发明人： Harry R. Bickford ,  Mark F. Bregman ,  Thomas M. Cipolla ,  John Gow, III ,  Peter G. Ledermann ,  Ekkehard F. Miersch ,  Leonard T. Olson ,  David P. Pagnani ,  Timothy C. Reiley ,  Uh-Po E. Tsou ,  Walter V. Vilkelis

IPC分类号： H01L21/60 ,  H01L23/495 ,  H01L23/498

CPC分类号： H01L24/50 ,  H01L23/49572 ,  H01L23/49861 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3011

摘要： Electronic device packaging structures useful for electrically interconnecting an electronic device to a substrate. The structure contains at least two metallization layers with dielectric layers between adjacent to metallization layers. The dielectric layers can have variable thickness. Beam leads can project inwardly in cantilevered fashion over a central aperture through the dielectric layers. The inner ends of the beam leads lie substantially in one plane and can be bonded to contact pads on integrated circuit electronic devices. Beam leads can project outwardly from the metallization layers over outer edges of the dielectric layers for bonding to contact pads on a substrate. Signal leads on metallization layers can be symmetrically arranged between ground and voltage leads to provide optimal impedance properties. These structures are useful for tape automated bonding applications.

公开(公告)号：US5189363A

公开(公告)日：1993-02-23

申请号：US583261

申请日：1990-09-14

申请人： Mark F. Bregman ,  Paul R. Hoffman ,  Peter G. Ledermann ,  Paul A. Moskowitz ,  Roger A. Pollak ,  Timothy C. Reiley ,  Mark B. Ritter

发明人： Mark F. Bregman ,  Paul R. Hoffman ,  Peter G. Ledermann ,  Paul A. Moskowitz ,  Roger A. Pollak ,  Timothy C. Reiley ,  Mark B. Ritter

IPC分类号： G01R31/26 ,  G01R1/073

CPC分类号： G01R1/0735

摘要： A system for testing chips uses a patterned tape having a patterned array of cantilevered contact leads. The tape serves as an interface between the chip under test and a testing unit by providing conductive leads from the I/O terminals on the chip to an off-chip measuring system. The leads on the array may have balls, tips or other shapes on the end to provide contact with the terminals and compensate for height differences. The tape is a single frame or has a series of arrays each positioned around an opening where the chip will be located when a particular pattern is positioned over that chip for test. The pattern on the tape may be the same array or a different array. The tape is indexed to a new pattern when the old one is damaged or no longer needed. Alignment with the chip is by optical sensing and physical pin movement. The tape may have a flap protruding into an aperture and deflectable to provide for planar contact of the leads to the device under test.

公开(公告)号：US4862322A

公开(公告)日：1989-08-29

申请号：US188805

申请日：1988-05-02

申请人： Harry R. Bickford ,  Mark F. Bregman ,  Paul A. Moskowitz ,  Michael J. Palmer ,  Timothy C. Reiley ,  Paige A. Poore ,  Caroline A. Kovac

发明人： Harry R. Bickford ,  Mark F. Bregman ,  Paul A. Moskowitz ,  Michael J. Palmer ,  Timothy C. Reiley ,  Paige A. Poore ,  Caroline A. Kovac

IPC分类号： H01L25/18 ,  H01L23/495 ,  H01L25/065 ,  H01L25/07

CPC分类号： H01L25/0657 ,  H01L23/49575 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2225/06513 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107

摘要： An integrated circuit device package in which integrated circuit devices are mounted with active faces placed facing each other to form a double-device structure. Input/output terminals on the active faces of each device can be electrically interconnected by placing an interconnection means between the chips to electrically interconnect input/output terminals on the active faces of the first and second device. Beam leads, each having an inner and outer lead bond site, project outwardly from between the devices where each of the inner lead bond site is solderlessly bonded between conducting patterns on each device bonded. A series of double-device structures can be formed on a tape having a plurality of sets of beam lead patterns thereon. Each beam lead of each set having an inner and outer lead bond site, projects outwardly from between the double-device structure, the inner lead bond site being solderlessly bonded between conducting patterns on each device.

公开(公告)号：US4814855A

公开(公告)日：1989-03-21

申请号：US857227

申请日：1986-04-29

申请人： Rodney T. Hodgson ,  Harry J. Jones ,  Peter G. Ledermann ,  Timothy C. Reiley ,  Paul A. Moskowitz

发明人： Rodney T. Hodgson ,  Harry J. Jones ,  Peter G. Ledermann ,  Timothy C. Reiley ,  Paul A. Moskowitz

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/538 ,  H05K3/40

CPC分类号： H01L24/86 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/75 ,  H01L2224/7565 ,  H01L2224/7965 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/207 ,  H01L2924/3025 ,  H05K3/4046 ,  H05K3/4092

摘要： Automated bonding of chips to tape and formation of bonding structures on Tape Automated Bonding (TAB) packaging structures are provided with bonding balls on the ends of beams leads of the TAB tape. Also balltape bonding balls are aligned on stacked TAB sheets and bonded together to form via interconnections through stacked balltape balls in multilayer, electronic packaging structures. Interconnection structures are provided for a universal chip connection laminate which can be applied between a chip and an MLC package. Area TAB tape, which comprises a modification of TAB tape provides balltape TAB connections by means of balltape bonds to areas within the interior of a chip whose leads are bonded in a TAB tape arrangement to the Inner Lead Bonds of the area tape.

摘要翻译： 芯片自动粘合到胶带上，并在胶带自动粘合（TAB）包装结构上形成粘合结构，在TAB胶带的光束引线的端部设有粘结球。 此外，球状粘结球在堆叠的TAB片上对准并且结合在一起，以通过多层电子包装结构中的堆叠球状球形成通孔互连。 为通用芯片连接层压板提供互连结构，其可应用于芯片和MLC封装之间。 包括TAB带的修改的区域TAB带通过球形连接提供球形TAB连接，该贴片连接到其引线以TAB带布置结合到区域带的内引线键的芯片内部的区域。

公开(公告)号：US4956605A

公开(公告)日：1990-09-11

申请号：US381623

申请日：1989-07-18

申请人： Harry R. Bickford ,  William L. Boland ,  Daniel P. Morris ,  Timothy C. Reiley

发明人： Harry R. Bickford ,  William L. Boland ,  Daniel P. Morris ,  Timothy C. Reiley

IPC分类号： G01R31/26 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66

CPC分类号： G01R31/2863 ,  H01L2924/0002

摘要： A TAB package comprises an elongated tape which has a plurality of sets of beam leads emplaced thereon and a plurality of electronic devices connected to the beam leads. At least a first beam lead of each set is connected to a common potential terminal on each device, and at least a second beam lead of each set is connected to a power terminal. A common potential bus is oriented along the elongated dimension of the tape and connects to the first beam leads, while a power bus is also oriented along the elongated dimension of the tape and is connected to the second beam leads. The application of power to the power bus and the simultaneous grounding of the common potential bus enables all electronic devices on the tape to be simultaneously energized and to be then subjected to an elevated temperature environment for static burn-in testing. To improve current conduction in the power and common potential buses, a tape comprising a non-conductive carrier and a pair of interposer/conductor tapes may be emplaced over the length of the tape bearing the chips. An additional spacer tape is then emplaced over the interposer tape and forces the interposer conductors into contact with the power and common potential buses.

公开(公告)号：US5134460A

公开(公告)日：1992-07-28

申请号：US609057

申请日：1990-11-02

申请人： Michael J. Brady ,  Sung K. Kang ,  Paul A. Moskowitz ,  James G. Ryan ,  Timothy C. Reiley ,  Erick G. Walton ,  Harry R. Bickford ,  Michael J. Palmer

发明人： Michael J. Brady ,  Sung K. Kang ,  Paul A. Moskowitz ,  James G. Ryan ,  Timothy C. Reiley ,  Erick G. Walton ,  Harry R. Bickford ,  Michael J. Palmer

IPC分类号： H01L21/60 ,  H01L23/485

CPC分类号： H01L24/86 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  Y10S257/915

摘要： A semiconductor chip carrying integrated circuits has lead lines terminating in conductive terminal pads exposed to the exterior through openings in a passivation layer. The pads include pedestals or bumps extending up from them. Each of the pedestals includes a thin metallic adhesion layer deposited on the pad. A thick metallic layer of aluminum or an alloy of aluminum is deposited upon said thin metallic adhesion layer. The thick metallic layer includes at least one metal selected from the group consisting of aluminum, aluminum plus a small percentage of Cu, Ni, Si, or Fe. Several other alternative metals can be added to aluminum to form an alloy. The thick metallic layer forms the bulk of the height of the pedestal. An adhesion layer is deposited on the bump of aluminum composed of a thin film of titanium or chromium. A barrier layer is deposited on the adhesion layer composed of copper, nickel, platinum, palladium or cobalt. A noble metal consisting of gold, palladium, or platinum is deposited on the barrier layer. In a variation of the top surface, a thick cap of a reworkable bonding metal is deposited above the metallic bump as the top surface of said bump. The bump can be composed of a number of metals such as gold, copper, nickel and aluminum in this case with aluminum being preferred. In place of the adhesion and barrier metals one can employ a layer of titanium nitride deposited on said thick layer of metal.

摘要翻译： 携带集成电路的半导体芯片具有终端于通过钝化层中的开口暴露于外部的导电端子焊盘中的导线。 垫片包括从它们向上延伸的基座或凸块。 每个基座包括沉积在垫上的薄金属粘附层。 铝的厚金属层或铝合金沉积在所述薄金属粘合层上。 厚金属层包括选自铝，铝和小百分比的Cu，Ni，Si或Fe中的至少一种金属。 可以将几种其它替代金属加入到铝中以形成合金。 厚的金属层形成基座的高度的大部分。 粘合层沉积在由钛或铬的薄膜构成的铝凸块上。 阻挡层沉积在由铜，镍，铂，钯或钴组成的粘合层上。 由金，钯或铂组成的贵金属沉积在阻挡层上。 在顶表面的变型中，可再加工的粘合金属的厚盖被沉积在金属凸块上方作为所述凸块的顶表面。 凸起可以由许多金属如金，铜，镍和铝组成，在这种情况下，优选铝。 代替粘合和阻挡金属，可以使用沉积在所述厚金属层上的氮化钛层。

公开(公告)号：US20090225464A1

公开(公告)日：2009-09-10

申请号：US12042230

申请日：2008-03-04

申请人： Jia-Yang Juang ,  Timothy C. Reiley ,  Timothy C. Strand

发明人： Jia-Yang Juang ,  Timothy C. Reiley ,  Timothy C. Strand

IPC分类号： G11B13/04 ,  G11B5/00 ,  G11B13/00

CPC分类号： G11B5/40 ,  G11B5/314 ,  G11B5/455 ,  G11B5/6064 ,  G11B5/607 ,  G11B2005/0005 ,  G11B2005/0021

摘要： An apparatus, system, and method for measuring thermally induced electric resistance changes in thermally assisted magnetic recording are disclosed for monitoring laser light output in thermally assisted magnetic recording disk drives. An electrical lead is coupled to a read/write head element. A first electrical resistance in the read/write head element is measured. The read/write head is heated by a laser and a second electrical resistance in the read/write head element is measured. The electrical resistance may be monitored at regular intervals when the read/write head element is on the ramp or the electrical resistance measurements may be continuously monitored as the read/write head flies over the magnetic media.

摘要翻译： 公开了一种用于测量热辅助磁记录中的热感应电阻变化的装置，系统和方法，用于监测热辅助磁记录盘驱动器中的激光输出。 电引线耦合到读/写头元件。 测量读/写头元件中的第一电阻。 读/写头被激光加热，并且测量读/写头元件中的第二电阻。 当读/写头元件在斜坡上时，可以以规则的间隔监视电阻，或者当读/写头飞越磁介质时可以连续监视电阻测量。

公开(公告)号：US06318624B1

公开(公告)日：2001-11-20

申请号：US09467731

申请日：1999-12-20

申请人： Surya Pattanaik ,  Timothy C. Reiley ,  Randall G. Simmons

发明人： Surya Pattanaik ,  Timothy C. Reiley ,  Randall G. Simmons

IPC分类号： B23K3514

CPC分类号： H05K3/3442 ,  H01L2224/1134 ,  H01L2224/16104 ,  H05K3/3494 ,  H05K2203/041 ,  H05K2203/107 ,  Y02P70/613 ,  Y10T29/49211

摘要： A solder balltape comprised of an elongated tail with a ball of solder formed at one end. A plurality of the balltape structures are positioned on a carrier strip of solder. The balltape is positioned in contact with a transducer pad on a magnetic read/write slider and an electrical lead pad. A pulse of focused laser radiation is directed at the ball part of the balltape and a right angle fillet joint is formed. A subsequent laser pulse or a sharpened blade is used to remove the tail from the newly formed fillet joint.

摘要翻译： 焊料球形体由细长的尾部组成，其一端形成有焊料球。 多个球形结构位于焊料载体条上。 球形电极定位成与磁读/写滑块和电引线板上的换能器垫接触。 聚焦激光辐射的脉冲指向球形球的球部，形成直角圆角接头。 随后的激光脉冲或锋利的刀片用于从新形成的圆角接头去除尾部。

公开(公告)号：US5148261A

公开(公告)日：1992-09-15

申请号：US646413

申请日：1991-01-28

申请人： Sung K. Kang ,  Michael J. Palmer ,  Timothy C. Reiley ,  Robert D. Topa

发明人： Sung K. Kang ,  Michael J. Palmer ,  Timothy C. Reiley ,  Robert D. Topa

IPC分类号： B23K20/02 ,  B23K20/233 ,  B23K33/00 ,  H01L21/603

CPC分类号： H01L24/80 ,  B23K20/023 ,  B23K20/233 ,  B23K33/00 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  Y10T428/12438

摘要： A contact member for thermocompression bonding in integrated circuit packaging has on a conductor end a uniform texture deformable layer with a hardness value in the range of that of soft gold which is approximately 90 on the Knoop scale and with a rough surface morphology having ridges with approximately 1 micrometer modulation frequency and a depth between ridges of from 1/4 to 1/2 that of the average integrated circuit pad. The deformable layer is produced by plating gold in a strong electronegative plating bath within a range of 0.03 to 0.05 mA/sq.mm. current density. Plating apparatus, for plating different areas, with different electronegative conditions, with separate independently powered anodes, is provided.

摘要翻译： 用于集成电路封装中的热压接的接触构件在导体端具有均匀的织构可变形层，硬度值在Knoop尺度上大约为90的软金的范围内，粗糙的表面形态具有大约 1微米调制频率和脊之间的深度为平均集成电路板的1/4至1/2。 可变形层通过在0.03-0.05mA / sq.mm的强电负极电镀浴中镀金而制成。 当前密度。 提供用于电镀不同区域的电镀装置，具有不同的电负性条件，具有单独的独立供电的阳极。

公开(公告)号：US4430690A

公开(公告)日：1984-02-07

申请号：US433329

申请日：1982-10-07

申请人： Dudley A. Chance ,  Chung W. Ho ,  Timothy C. Reiley

发明人： Dudley A. Chance ,  Chung W. Ho ,  Timothy C. Reiley

IPC分类号： H01G2/06 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30 ,  H05K3/34 ,  H01G1/01 ,  H01G3/06

CPC分类号： H05K3/3442 ,  H01G4/30 ,  H05K2201/09663 ,  Y02P70/613 ,  Y10T29/435

摘要： A laminated capacitor is joined to the surface of a chip carrier for large scale integrated circuit chips. The capacitor lies adjacent to positions where chips are located. The capacitor includes a plurality of capacitor plates. The capacitor is bonded to the chip carrier with an array of solder bars comprising an elongated strip of metallic material. Each of the bars is connected to a set of the capacitor plates in the laminated capacitor by means of tab connections on the plates, whereby each of the plates is connected by a plurality of tabs to a plurality of the solder bars. Methods of fabrication of the laminated capacitor structure and solder bars are described.

摘要翻译： 叠层电容器连接到用于大规模集成电路芯片的芯片载体的表面。 电容器位于芯片位置附近。 电容器包括多个电容器板。 电容器通过包括细长的金属材料条的焊料棒阵列结合到芯片载体上。 每个棒通过板上的接头连接件连接到层压电容器中的一组电容器板，由此每个板通过多个接片连接到多个焊料条。 描述了层压电容器结构和焊料棒的制造方法。