公开(公告)号：US5134460A

公开(公告)日：1992-07-28

申请号：US609057

申请日：1990-11-02

申请人： Michael J. Brady ,  Sung K. Kang ,  Paul A. Moskowitz ,  James G. Ryan ,  Timothy C. Reiley ,  Erick G. Walton ,  Harry R. Bickford ,  Michael J. Palmer

发明人： Michael J. Brady ,  Sung K. Kang ,  Paul A. Moskowitz ,  James G. Ryan ,  Timothy C. Reiley ,  Erick G. Walton ,  Harry R. Bickford ,  Michael J. Palmer

IPC分类号： H01L21/60 ,  H01L23/485

CPC分类号： H01L24/86 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  Y10S257/915

摘要： A semiconductor chip carrying integrated circuits has lead lines terminating in conductive terminal pads exposed to the exterior through openings in a passivation layer. The pads include pedestals or bumps extending up from them. Each of the pedestals includes a thin metallic adhesion layer deposited on the pad. A thick metallic layer of aluminum or an alloy of aluminum is deposited upon said thin metallic adhesion layer. The thick metallic layer includes at least one metal selected from the group consisting of aluminum, aluminum plus a small percentage of Cu, Ni, Si, or Fe. Several other alternative metals can be added to aluminum to form an alloy. The thick metallic layer forms the bulk of the height of the pedestal. An adhesion layer is deposited on the bump of aluminum composed of a thin film of titanium or chromium. A barrier layer is deposited on the adhesion layer composed of copper, nickel, platinum, palladium or cobalt. A noble metal consisting of gold, palladium, or platinum is deposited on the barrier layer. In a variation of the top surface, a thick cap of a reworkable bonding metal is deposited above the metallic bump as the top surface of said bump. The bump can be composed of a number of metals such as gold, copper, nickel and aluminum in this case with aluminum being preferred. In place of the adhesion and barrier metals one can employ a layer of titanium nitride deposited on said thick layer of metal.

摘要翻译： 携带集成电路的半导体芯片具有终端于通过钝化层中的开口暴露于外部的导电端子焊盘中的导线。 垫片包括从它们向上延伸的基座或凸块。 每个基座包括沉积在垫上的薄金属粘附层。 铝的厚金属层或铝合金沉积在所述薄金属粘合层上。 厚金属层包括选自铝，铝和小百分比的Cu，Ni，Si或Fe中的至少一种金属。 可以将几种其它替代金属加入到铝中以形成合金。 厚的金属层形成基座的高度的大部分。 粘合层沉积在由钛或铬的薄膜构成的铝凸块上。 阻挡层沉积在由铜，镍，铂，钯或钴组成的粘合层上。 由金，钯或铂组成的贵金属沉积在阻挡层上。 在顶表面的变型中，可再加工的粘合金属的厚盖被沉积在金属凸块上方作为所述凸块的顶表面。 凸起可以由许多金属如金，铜，镍和铝组成，在这种情况下，优选铝。 代替粘合和阻挡金属，可以使用沉积在所述厚金属层上的氮化钛层。

公开(公告)号：US4840302A

公开(公告)日：1989-06-20

申请号：US181882

申请日：1988-04-15

申请人： David A. Gardner ,  James G. Ryan ,  Joseph G. Schaefer ,  Erick G. Walton

发明人： David A. Gardner ,  James G. Ryan ,  Joseph G. Schaefer ,  Erick G. Walton

IPC分类号： H01L21/60 ,  H01L23/485

CPC分类号： H01L24/11 ,  H01L24/02 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/19043 ,  Y10T428/12458 ,  Y10T428/12528 ,  Y10T428/12583

摘要： An alloy for contacting portions of a conductive interconnect layer exposed by an overlying organic insulating layer having apertures therethrough. The alloy contains chromium and titanium, and is formed such that at least 50 atm % of the total content of the alloy is titanium at the alloy-insulating layer interface.

公开(公告)号：US5251806A

公开(公告)日：1993-10-12

申请号：US870647

申请日：1992-04-16

申请人： Birendra N. Agarwala ,  Aziz M. Ahsan ,  Arthur Bross ,  Mark F. Chadurjian ,  Nicholas G. Koopman ,  Li-Chung Lee ,  Karl J. Puttlitz ,  Sudipta K. Ray ,  James G. Ryan ,  Joseph G. Schaefer ,  Kamalesh K. Srivastava ,  Paul A. Totta ,  Erick G. Walton ,  Adolf E. Wirsing

发明人： Birendra N. Agarwala ,  Aziz M. Ahsan ,  Arthur Bross ,  Mark F. Chadurjian ,  Nicholas G. Koopman ,  Li-Chung Lee ,  Karl J. Puttlitz ,  Sudipta K. Ray ,  James G. Ryan ,  Joseph G. Schaefer ,  Kamalesh K. Srivastava ,  Paul A. Totta ,  Erick G. Walton ,  Adolf E. Wirsing

IPC分类号： H01L21/60 ,  H01L23/485 ,  H05K3/34 ,  H01L21/283

CPC分类号： H01L24/12 ,  H01L24/11 ,  H01L2224/11901 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13669 ,  H01L2224/1367 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/13676 ,  H01L2224/13679 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L24/16 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15787 ,  H05K3/3431 ,  H05K3/3457

摘要： The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.

摘要翻译： 本发明一般涉及新的互连及其制造方法，更具体地说，涉及一种细长的焊料互连及其制造方法。 在电子载体上，形成焊盘，在其上沉积焊料块并用金属层封盖，从而形成细长的焊料互连。 现在可以通过在已经被金属层覆盖的第一焊料块上形成第二焊料块来形成另外细长的焊料互连。 可以通过用金属覆盖层封盖前述焊料块和/或最后的焊料块来形成附加的细长焊料互连。 或者，封装层可以是形成在焊料块的侧壁上的侧壁间隔物的形式。

公开(公告)号：US5130779A

公开(公告)日：1992-07-14

申请号：US540256

申请日：1990-06-19

申请人： Birendra N. Agarwala ,  Aziz M. Ahsan ,  Arthur Bross ,  Mark F. Chadurjian ,  Nicholas G. Koopman ,  Li-Chung Lee ,  Karl J. Puttlitz ,  Sudipta K. Ray ,  James G. Ryan ,  Joseph G. Schaefer ,  Kamalesh K. Srivastava ,  Paul A. Totta ,  Erick G. Walton ,  Adolf E. Wirsing

发明人： Birendra N. Agarwala ,  Aziz M. Ahsan ,  Arthur Bross ,  Mark F. Chadurjian ,  Nicholas G. Koopman ,  Li-Chung Lee ,  Karl J. Puttlitz ,  Sudipta K. Ray ,  James G. Ryan ,  Joseph G. Schaefer ,  Kamalesh K. Srivastava ,  Paul A. Totta ,  Erick G. Walton ,  Adolf E. Wirsing

IPC分类号： H01L21/60 ,  H01L23/485 ,  H05K3/34

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13669 ,  H01L2224/1367 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/13676 ,  H01L2224/13679 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15787 ,  H05K3/3431 ,  H05K3/3457

摘要： The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.

摘要翻译： 本发明一般涉及新的互连及其制造方法，更具体地说，涉及一种细长的焊料互连及其制造方法。 在电子载体上，形成焊盘，在其上沉积焊料块并用金属层封盖，从而形成细长的焊料互连。 现在可以通过在已经被金属层覆盖的第一焊料块上形成第二焊料块来形成另外细长的焊料互连。 可以通过用金属覆盖层封盖前述焊料块和/或最后的焊料块来形成附加的细长焊料互连。 或者，封装层可以是形成在焊料块的侧壁上的侧壁间隔物的形式。

公开(公告)号：US07207096B2

公开(公告)日：2007-04-24

申请号：US10707896

申请日：2004-01-22

申请人： Jeffrey P. Gambino ,  William T. Motsiff ,  Erick G. Walton

发明人： Jeffrey P. Gambino ,  William T. Motsiff ,  Erick G. Walton

IPC分类号： H01F7/127 ,  H01L21/44

CPC分类号： H01L28/10 ,  H01F41/041 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/3192 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/02 ,  H01L2224/0401 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  Y10T29/4902 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method for manufacturing high performance copper inductors includes providing a tall, Cu laminate spiral inductor is formed at the last metal level, and at the last metal +1 level, with the metal levels being interconnected by a bar via having the same spiral shape as the spiral metal inductors at the last metal level and the last metal +1 level. The method includes integrating the formation of thick inductors with the formation of bond pads, terminals and interconnect wiring with the last metal +1 wiring. Included are dielectric deposition and spacer formation steps, and/or selective deposition of a passivating metal such as CoWP, to passivate a Cu inductor that is formed after the last metal layer.

摘要翻译： 一种用于制造高性能铜电感器的方法包括提供在最后的金属层面上形成的高Cu层压螺旋电感器，并且在最后的金属+1级别处，金属层通过棒与第二金属层相互螺旋形形成 最后一个金属级螺旋金属电感和最后一个金属+1电平。 该方法包括将厚电感器的形成与最后的金属+1布线形成接合焊盘，端子和互连布线。 包括介电沉积和间隔物形成步骤，和/或钝化金属如CoWP的选择性沉积，以钝化在最后一个金属层之后形成的Cu电感器。

公开(公告)号：US06471845B1

公开(公告)日：2002-10-29

申请号：US09461849

申请日：1999-12-15

申请人： John O. Dukovic ,  William E. Corbin, Jr. ,  Erick G. Walton ,  Peter S. Locke ,  Panayotis C. Andricacos ,  James E. Fluegel ,  Evan Patton ,  Jonathan Reid

发明人： John O. Dukovic ,  William E. Corbin, Jr. ,  Erick G. Walton ,  Peter S. Locke ,  Panayotis C. Andricacos ,  James E. Fluegel ,  Evan Patton ,  Jonathan Reid

IPC分类号： C25D2112

CPC分类号： C25D21/12 ,  Y10T137/2509

摘要： A method for controlling the composition of a chemical bath in which predictive dosing is used to account for changes in the composition of the bath in which the operating characteristics of the process are partitioned into a plurality of operating modes and the consumption or generation of materials related to the process are determined empirically and additions of material are made as appropriate.

摘要翻译： 用于控制化学浴的组成的方法，其中使用预测剂量来解释浴的组成的变化，其中过程的操作特性被划分为多种操作模式以及相关材料的消耗或产生 根据经验确定该过程，并酌情添加材料。

公开(公告)号：US5760674A

公开(公告)日：1998-06-02

申请号：US563691

申请日：1995-11-28

申请人： Richard A. Gilmour ,  Ronald R. Uttecht ,  Erick G. Walton

发明人： Richard A. Gilmour ,  Ronald R. Uttecht ,  Erick G. Walton

IPC分类号： H01L23/525 ,  H01H85/00

CPC分类号： H01L23/5258 ,  H01L2924/0002

摘要： The fuse link includes a first and second interconnect, with interconnects each being substantially longer than deep. The interconnects are disposed toward each other with a insulator region between them. A fusible conductor, spanning the insulator region, is attached at the top of the interconnects. The present device allows the length of the fusible conductor to be shortened, and results in a fuse link that can be consistently blown with a single laser pulse. Additionally, the fuse link can be used in a staggered layout. The staggered layout of parallel fuse links allows a high number of links in a relatively small area, with or without the use of tungsten barriers, and allows accessing all fuse links through a single fuse blow window.

摘要翻译： 熔丝连接件包括第一和第二互连件，其互连件基本上比深度长。 互连通过它们之间的绝缘体区域彼此相对设置。 跨越绝缘体区域的可熔导体连接在互连的顶部。 本装置允许可熔导体的长度缩短，并且导致可以用单个激光脉冲一致地熔断的熔丝链。 此外，熔丝链可以以交错的布局使用。 平行熔丝链的交错布局允许在有或没有使用钨屏障的情况下，在相对较小的区域中有大量的连接，并且允许通过单个保险丝熔断窗口访问所有熔丝链。

公开(公告)号：US20100051474A1

公开(公告)日：2010-03-04

申请号：US12548893

申请日：2009-08-27

申请人： Panayotis C. Andricacos ,  Caliopi Andricacos ,  Donald F. Canaperi ,  Emanuel I. Cooper ,  John M. Cotte ,  Hariklia Deligianni ,  Laertis Economikos ,  Daniel C. Edelstein ,  Silvia Franz ,  Balasubramanian Pranatharthiharan ,  Mahadevaiyer Krishnan ,  Andrew P. Mansson ,  Erick G. Walton ,  Alan C. West

发明人： Panayotis C. Andricacos ,  Caliopi Andricacos ,  Donald F. Canaperi ,  Emanuel I. Cooper ,  John M. Cotte ,  Hariklia Deligianni ,  Laertis Economikos ,  Daniel C. Edelstein ,  Silvia Franz ,  Balasubramanian Pranatharthiharan ,  Mahadevaiyer Krishnan ,  Andrew P. Mansson ,  Erick G. Walton ,  Alan C. West

IPC分类号： B23H5/06

CPC分类号： C25F3/02 ,  B23H5/08 ,  C09G1/04 ,  H01L21/32125

摘要： Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.

摘要翻译： 提供了诸如铜之类的硅芯片互连材料的电化学机械抛光（e-CMP）的方法和组合物。 所述方法包括使用根据本发明的组合物与具有各种构型的垫组合。

公开(公告)号：US07015580B2

公开(公告)日：2006-03-21

申请号：US10722704

申请日：2003-11-25

申请人： John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Erick G. Walton

发明人： John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Erick G. Walton

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/85 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4807 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85345 ,  H01L2224/85365 ,  H01L2224/85385 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00015

摘要： An intermediate semiconductor structure and method for low-pressure wire bonding that reduces the propensity of dielectric material to mechanical failure due to any wire bonding stresses. Roughened surfaces such as metal pillars or metal dendrites are provided on a bonding pad, bonding wire or both. These roughened surfaces increase reactivity between the bond wire and the bond pad to form strong bonds. This increased activity as a result of the roughened bonding pad and/or wire surfaces reduce the amount of pressure, temperature and energy required for wire bonding, which in turn, avoids damage to the bonding pad as well as the semiconductor substrate.

摘要翻译： 用于低压引线接合的中间半导体结构和方法，其降低由于任何引线键合应力引起的介电材料对机械故障的倾向。 在焊盘，接合线或两者上设置诸如金属柱或金属枝晶的粗化表面。 这些粗糙表面增加了接合线和接合焊盘之间的反应性，以形成强键。 由于粗糙的焊盘和/或线表面的结果，这种增加的活性减少了引线接合所需的压力，温度和能量的量，这进而避免了对焊盘以及半导体衬底的损坏。

公开(公告)号：US5420455A

公开(公告)日：1995-05-30

申请号：US221715

申请日：1994-03-31

申请人： Richard A. Gilmour ,  Thomas J. Hartswick ,  David C. Thomas ,  Ronald R. Uttecht ,  Erick G. Walton

发明人： Richard A. Gilmour ,  Thomas J. Hartswick ,  David C. Thomas ,  Ronald R. Uttecht ,  Erick G. Walton

IPC分类号： H01L23/62 ,  H01L27/02

CPC分类号： H01L23/62 ,  H01L2924/0002

摘要： The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated circuit the barriers are non-frangible, high melting point structures buried in the passivating layer, covering a wiring layer containing a fuse, and are between the fuse and adjacent circuit elements in the wiring layer structures.Also taught is a method of protecting circuit elements adjacent a fuse comprising the steps of depositing an insulating layer on the surface of a semiconductor device having active regions therein, forming a plurality of fuses and circuit elements in said layer, coating said fuses and elements with a second insulating layer, patterning said second insulating layer to form grooves between each of said fuses and any adjacent fuse or circuit element, and depositing a high melting point and non-frangible material in said grooves.

摘要翻译： 本公开提出了一种改进的集成电路，其中与保险丝相邻的电路元件由位于保险丝附近的屏障保护。 在改进的集成电路中，阻挡层是非易碎的，高熔点结构掩埋在钝化层中，覆盖包含保险丝的布线层，并且位于布线层结构中的熔丝和相邻的电路元件之间。 还教导了一种保护靠近熔丝的电路元件的方法，包括以下步骤：在其中具有有源区的半导体器件的表面上沉积绝缘层，在所述层中形成多个保险丝和电路元件，将所述保险丝和元件涂覆 第二绝缘层，图案化所述第二绝缘层以在每个所述保险丝和任何相邻的熔丝或电路元件之间形成槽，以及在所述槽中沉积高熔点和非易碎材料。