公开(公告)号：US09941196B2

公开(公告)日：2018-04-10

申请号：US15130904

申请日：2016-04-15

申请人： Ho-Jin Lee ,  Tae-Je Cho ,  Dong-Hyeon Jang ,  Ho-Geon Song ,  Se-Young Jeong ,  Un-Byoung Kang ,  Min-Seung Yoon

发明人： Ho-Jin Lee ,  Tae-Je Cho ,  Dong-Hyeon Jang ,  Ho-Geon Song ,  Se-Young Jeong ,  Un-Byoung Kang ,  Min-Seung Yoon

IPC分类号： H01L21/768 ,  H01L23/498 ,  H01L23/48 ,  H01L25/065 ,  H01L23/525

CPC分类号： H01L23/49844 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311

摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

公开(公告)号：US08592991B2

公开(公告)日：2013-11-26

申请号：US13235369

申请日：2011-09-17

申请人： Ho-Jin Lee ,  Tae-Je Cho ,  Dong-Hyeon Jang ,  Ho-Geon Song ,  Se-Young Jeong ,  Un-Byoung Kang ,  Min-Seung Yoon

发明人： Ho-Jin Lee ,  Tae-Je Cho ,  Dong-Hyeon Jang ,  Ho-Geon Song ,  Se-Young Jeong ,  Un-Byoung Kang ,  Min-Seung Yoon

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/00

CPC分类号： H01L23/49844 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311

摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

摘要翻译： 在一个实施例中，半导体器件包括具有第一表面的半导体衬底和与第一表面相对的第二表面。 第二表面限定再分布沟槽。 基板具有贯穿其中的通孔。 半导体器件还包括设置在通孔中的贯通孔。 通孔可以包括依次形成在通孔的内壁上的通孔绝缘层，阻挡层。 通孔还可以包括邻近阻挡层的导电连接器。 半导体器件还包括形成在衬底的第二表面上的绝缘层图案。 绝缘层图案限定了暴露通孔的顶表面的区域的开口。 半导体器件包括设置在沟槽中并与通孔电连接的再分配层。 绝缘层图案与导电连接器的区域重叠。

公开(公告)号：US07884392B2

公开(公告)日：2011-02-08

申请号：US12362210

申请日：2009-01-29

申请人： Hyuek-Jae Lee ,  Tae-Je Cho ,  Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Woon-Seong Kwon ,  Hyung-Sun Jang

发明人： Hyuek-Jae Lee ,  Tae-Je Cho ,  Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Woon-Seong Kwon ,  Hyung-Sun Jang

IPC分类号： H01L31/0328

CPC分类号： H01L27/14623 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2224/02372 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05023 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2224/05099

摘要： One embodiment exemplarily described herein can be characterized as an image sensor including a substrate having a front surface and a rear surface; a photoelectric converting portion on the front surface of the substrate; a through via extending through the substrate, wherein the through via is electrically connected to the photoelectric converting portion; an external connection terminal on the rear surface of the substrate, wherein the external connection terminal is connected to the through via; and a light shading layer formed on a portion of the rear surface of the substrate, wherein the light shading layer is substantially opaque with respect to an external light. In some embodiments, the portion of the rear surface of the substrate on which the light shading layer is formed is not overlapped by the through via or the external connection terminal.

摘要翻译： 本文示例性描述的一个实施例可以被表征为包括具有前表面和后表面的基板的图像传感器; 在所述基板的前表面上的光电转换部; 贯穿所述基板延伸的通孔，其中所述通孔电连接到所述光电转换部分; 在所述基板的后表面上的外部连接端子，其中所述外部连接端子连接到所述通孔; 以及形成在所述基板的后表面的一部分上的遮光层，其中所述遮光层相对于外部光基本上是不透明的。 在一些实施例中，其上形成有遮光层的基板的后表面的部分不与通孔或外部连接端子重叠。

公开(公告)号：US08114701B2

公开(公告)日：2012-02-14

申请号：US12274642

申请日：2008-11-20

申请人： Woon-Seong Kwon ,  Tae-Je Cho ,  Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Hyung-Sun Jang

发明人： Woon-Seong Kwon ,  Tae-Je Cho ,  Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Hyung-Sun Jang

IPC分类号： H01L21/00

CPC分类号： H04N5/2252 ,  H01L27/14618 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H04N5/2253 ,  H04N5/2257 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： Provided are camera modules capable of effectively shielding electromagnetic (EM) waves and methods of fabricating the same. A method of fabricating a camera module includes, preparing a first wafer including an array of lens units. Then, a second wafer including an array of image sensor CSPs (chip-scale packages) is prepared. Each of the image sensor CSPs includes an image sensor chip corresponding to one of the lens units. The first wafer is stacked on the second wafer. The first wafer and the second wafer are cut to form a trench exposing the top surface of the image sensor chip at the interface between adjacent lens units. The trench is filled with a first material used for forming a housing. The first material and the image sensor chip are cut at the interface between the adjacent lens units.

摘要翻译： 提供能够有效屏蔽电磁波（EM）波的相机模块及其制造方法。 制造相机模块的方法包括：制备包括透镜单元阵列的第一晶片。 然后，制备包括图像传感器CSP阵列（芯片级封装）的第二晶片。 图像传感器CSP中的每一个包括对应于一个透镜单元的图像传感器芯片。 第一晶片被堆叠在第二晶片上。 切割第一晶片和第二晶片以形成在相邻透镜单元之间的界面处暴露图像传感器芯片的顶表面的沟槽。 沟槽填充有用于形成壳体的第一材料。 第一材料和图像传感器芯片在相邻透镜单元之间的界面处被切割。

公开(公告)号：US09601465B2

公开(公告)日：2017-03-21

申请号：US14509317

申请日：2014-10-08

申请人： Un-Byoung Kang ,  Tae-Je Cho ,  Byung-Hyug Roh

发明人： Un-Byoung Kang ,  Tae-Je Cho ,  Byung-Hyug Roh

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06131 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1413 ,  H01L2224/14181 ,  H01L2224/16113 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1713 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014

摘要： A chip-stacked semiconductor package includes a first chip having a first front surface, a first back surface, and a first connection member on the first front surface, the first back surface being opposite to the first front surface; a second chip having a second front surface, a second back surface, a second connection member and a first through-silicon via (TSV) electrically connected to the second connection member, the second back surface opposite to the second front surface, and the second connection member on the second front face; and a first sealing member between the first front surface and the second front surface, the first sealing member filling a space between the first connection member and the second connection member, the first connection member of the first chip and the second connection member of the second chip being symmetric with respect to each other.

公开(公告)号：US08466527B2

公开(公告)日：2013-06-18

申请号：US12915157

申请日：2010-10-29

申请人： Hyung-Sun Jang ,  Woon-Seong Kwon ,  Tae-Je Cho ,  Un-Byoung Kang ,  Jung-Hwan Kim

发明人： Hyung-Sun Jang ,  Woon-Seong Kwon ,  Tae-Je Cho ,  Un-Byoung Kang ,  Jung-Hwan Kim

IPC分类号： H01L31/0232

CPC分类号： H01L31/18 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2224/13

摘要： A semiconductor package and a method for manufacturing the same are provided. The semiconductor package includes a semiconductor chip having a first surface, a second surface and a pixel area, first adhesion patterns disposed on the first surface, second adhesion patterns disposed between the first adhesion patterns and the pixel area and disposed on the first surface, and external connection terminals disposed on the second surface, wherein the second adhesion patterns and the external connection terminals are disposed to overlap each other.

摘要翻译： 提供半导体封装及其制造方法。 半导体封装包括具有第一表面，第二表面和像素区域的半导体芯片，设置在第一表面上的第一粘附图案，设置在第一粘附图案和像素区域之间并设置在第一表面上的第二粘合图案，以及 设置在第二表面上的外部连接端子，其中第二粘合图案和外部连接端子彼此重叠设置。

公开(公告)号：US20110180892A1

公开(公告)日：2011-07-28

申请号：US12915157

申请日：2010-10-29

申请人： Hyung-Sun JANG ,  Woon-Seong Kwon ,  Tae-Je Cho ,  Un-Byoung Kang ,  Jung-Hwan Kim

发明人： Hyung-Sun JANG ,  Woon-Seong Kwon ,  Tae-Je Cho ,  Un-Byoung Kang ,  Jung-Hwan Kim

IPC分类号： H01L31/0232 ,  H01L31/0203

CPC分类号： H01L31/18 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2224/13

摘要： A semiconductor package and a method for manufacturing the same are provided. The semiconductor package includes a semiconductor chip having a first surface, a second surface and a pixel area, first adhesion patterns disposed on the first surface, second adhesion patterns disposed between the first adhesion patterns and the pixel area and disposed on the first surface, and external connection terminals disposed on the second surface, wherein the second adhesion patterns and the external connection terminals are disposed to overlap each other.

摘要翻译： 提供半导体封装及其制造方法。 半导体封装包括具有第一表面，第二表面和像素区域的半导体芯片，设置在第一表面上的第一粘附图案，设置在第一粘附图案和像素区域之间并设置在第一表面上的第二粘合图案，以及 设置在第二表面上的外部连接端子，其中第二粘合图案和外部连接端子彼此重叠设置。

公开(公告)号：US08643179B2

公开(公告)日：2014-02-04

申请号：US13240302

申请日：2011-09-22

申请人： Yun-Hyeok Im ,  Jong-Yeon Kim ,  Tae-Je Cho ,  Un-Byoung Kang

发明人： Yun-Hyeok Im ,  Jong-Yeon Kim ,  Tae-Je Cho ,  Un-Byoung Kang

IPC分类号： H01L23/485

CPC分类号： H01L24/81 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/11001 ,  H01L2224/13025 ,  H01L2224/13075 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00

摘要： Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.

摘要翻译： 提供一种凸块结构，包括第一凸块和第二凸块，包括该凸块的半导体封装及其制造方法。 凸块结构包括：设置在基板的连接焊盘上的第一凸块，所述第一凸块包括从所述连接焊盘延伸的多个纳米线和连接所述多个纳米线的端部的主体; 以及设置在第一凸块的主体上的第二凸块。

公开(公告)号：US20120156823A1

公开(公告)日：2012-06-21

申请号：US13281870

申请日：2011-10-26

申请人： Jong-Yun MYUNG ,  Hyuek-Jae Lee ,  Ji-Sun Hong ,  Tae-Je Cho ,  Un-Byoung Kang ,  Hyung-Sun Jang ,  Eun-Mi Kim ,  Jung-Hwan Kim ,  Tae-Hong Min

发明人： Jong-Yun MYUNG ,  Hyuek-Jae Lee ,  Ji-Sun Hong ,  Tae-Je Cho ,  Un-Byoung Kang ,  Hyung-Sun Jang ,  Eun-Mi Kim ,  Jung-Hwan Kim ,  Tae-Hong Min

IPC分类号： H01L31/18 ,  H01L21/50 ,  H01L21/78

CPC分类号： H01L21/78 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/1464 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12043 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00

摘要： A method of forming a semiconductor device includes preparing a semiconductor substrate having a plurality of chips formed thereon and a scribe lane disposed between the chips, simultaneously forming a groove having a first depth in the scribe lane, and a through hole penetrating the chips and having a second depth. The chips are separated along the groove. The first depth is smaller than the second depth.

摘要翻译： 一种形成半导体器件的方法包括制备其上形成有多个芯片的半导体衬底和设置在芯片之间的划线，同时形成在划线中具有第一深度的凹槽，以及穿透芯片的通孔，并具有 第二个深度。 芯片沿凹槽分开。 第一深度小于第二深度。

公开(公告)号：US08563349B2

公开(公告)日：2013-10-22

申请号：US13281870

申请日：2011-10-26

申请人： Jong-Yun Myung ,  Hyuek-Jae Lee ,  Ji-Sun Hong ,  Tae-Je Cho ,  Un-Byoung Kang ,  Hyung-Sun Jang ,  Eun-Mi Kim ,  Jung-Hwan Kim ,  Tae-Hong Min

发明人： Jong-Yun Myung ,  Hyuek-Jae Lee ,  Ji-Sun Hong ,  Tae-Je Cho ,  Un-Byoung Kang ,  Hyung-Sun Jang ,  Eun-Mi Kim ,  Jung-Hwan Kim ,  Tae-Hong Min

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/1464 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12043 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00

摘要： A method of forming a semiconductor device includes preparing a semiconductor substrate having a plurality of chips formed thereon and a scribe lane disposed between the chips, simultaneously forming a groove having a first depth in the scribe lane, and a through hole penetrating the chips and having a second depth. The chips are separated along the groove. The first depth is smaller than the second depth.

摘要翻译： 一种形成半导体器件的方法包括制备其上形成有多个芯片的半导体衬底和设置在芯片之间的划线，同时形成在划线中具有第一深度的凹槽，以及穿透芯片的通孔，并具有 第二个深度。 芯片沿凹槽分开。 第一深度小于第二深度。