公开(公告)号：US08637969B2

公开(公告)日：2014-01-28

申请号：US13908728

申请日：2013-06-03

申请人： Teak-hoon Lee ,  Won-keun Kim ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im

发明人： Teak-hoon Lee ,  Won-keun Kim ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L23/49811 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/1811 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first cutting groove; and forming a second cutting groove having a second kerf width that is less than the first kerf width, in the molding layer, so as to separate the molding layer into individual molding layers covering one of the plurality of first semiconductor chips and corresponding one of the plurality of second semiconductor chips.

摘要翻译： 一种形成具有大容量和减小或最小化体积的半导体封装的方法包括：使用粘合剂层将半导体衬底附着在支撑衬底上，其中半导体衬底包括多个第一半导体芯片和切屑区域，其中 多个第一半导体芯片中的第一和第二半导体芯片通过芯片切割区域彼此分离，并且半导体衬底包括其上形成有源区域的第一表面和与第一表面相对的第二表面; 在所述多个第一半导体芯片中的第一和第二半导体芯片之间形成具有第一切口宽度的第一切割槽，使得半导体基板被分离成多个第一半导体芯片; 分别将对应于第一半导体芯片的多个第二半导体芯片附着到多个第一半导体芯片; 形成模塑层以填充第一切割槽; 以及在成形层中形成具有小于第一切口宽度的第二切口宽度的第二切割槽，以将模制层分离成覆盖多个第一半导体芯片中的一个的各个成型层和相应的一个 多个第二半导体芯片。

公开(公告)号：US08637350B2

公开(公告)日：2014-01-28

申请号：US13439447

申请日：2012-04-04

申请人： Jung-seok Ahn ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im ,  Chang-seong Jeon ,  Teak-hoon Lee ,  Sang-sick Park

发明人： Jung-seok Ahn ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im ,  Chang-seong Jeon ,  Teak-hoon Lee ,  Sang-sick Park

IPC分类号： H01L21/00

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/92125 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

摘要翻译： 一种制造芯片堆叠的半导体封装的方法，所述方法包括制备包括多个第一芯片的基片，每个第一芯片均具有穿硅通孔（TSV）; 将包括多个第一芯片的基底晶片接合到支撑载体; 准备多个第二芯片; 通过将所述多个第二芯片接合到所述多个第一芯片来形成堆叠的芯片; 用密封部分密封堆叠的芯片; 并将堆叠的芯片彼此分离。

公开(公告)号：US08592991B2

公开(公告)日：2013-11-26

申请号：US13235369

申请日：2011-09-17

申请人： Ho-Jin Lee ,  Tae-Je Cho ,  Dong-Hyeon Jang ,  Ho-Geon Song ,  Se-Young Jeong ,  Un-Byoung Kang ,  Min-Seung Yoon

发明人： Ho-Jin Lee ,  Tae-Je Cho ,  Dong-Hyeon Jang ,  Ho-Geon Song ,  Se-Young Jeong ,  Un-Byoung Kang ,  Min-Seung Yoon

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/00

CPC分类号： H01L23/49844 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311

摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

摘要翻译： 在一个实施例中，半导体器件包括具有第一表面的半导体衬底和与第一表面相对的第二表面。 第二表面限定再分布沟槽。 基板具有贯穿其中的通孔。 半导体器件还包括设置在通孔中的贯通孔。 通孔可以包括依次形成在通孔的内壁上的通孔绝缘层，阻挡层。 通孔还可以包括邻近阻挡层的导电连接器。 半导体器件还包括形成在衬底的第二表面上的绝缘层图案。 绝缘层图案限定了暴露通孔的顶表面的区域的开口。 半导体器件包括设置在沟槽中并与通孔电连接的再分配层。 绝缘层图案与导电连接器的区域重叠。

公开(公告)号：US08586477B2

公开(公告)日：2013-11-19

申请号：US13195128

申请日：2011-08-01

申请人： Se-young Jeong ,  Ho-jin Lee ,  Ho-geon Song ,  Jae-hyun Phee

发明人： Se-young Jeong ,  Ho-jin Lee ,  Ho-geon Song ,  Jae-hyun Phee

IPC分类号： H01L21/44 ,  H01L21/00 ,  H01L23/04

CPC分类号： H01L21/76898 ,  H01L21/563 ,  H01L23/481 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2224/05609 ,  H01L2224/05613 ,  H01L2224/05614 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05683 ,  H01L2224/05684 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13171 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05552

摘要： A semiconductor apparatus having a through electrode, a semiconductor package, and a method of manufacturing the semiconductor package are provided. The method of includes preparing a substrate including a buried via, the buried via having a first surface at a first end, and the buried via extending from a first substrate surface of the substrate into the substrate; planarizing a second substrate surface of the substrate opposite the first substrate surface to form a through via by exposing a second via surface at a second end of the buried via opposite the first end; forming a conductive capping layer on the exposed second via surface of the through via; and recessing the second substrate surface so that at least a first portion of the through via extends beyond the second substrate surface.

摘要翻译： 提供了具有贯通电极，半导体封装以及半导体封装的制造方法的半导体装置。 该方法包括制备包括掩埋通孔的衬底，所述埋入通孔在第一端具有第一表面，以及所述掩埋通孔从所述衬底的第一衬底表面延伸到所述衬底中; 平行化与第一衬底表面相对的衬底的第二衬底表面以通过在与第一端相对的埋置通孔的第二端处暴露第二通孔表面而形成通孔; 在通孔的暴露的第二通孔表面上形成导电覆盖层; 并且使所述第二衬底表面凹陷，使得所述通孔的至少第一部分延伸超出所述第二衬底表面。

公开(公告)号：US20120234497A1

公开(公告)日：2012-09-20

申请号：US13418795

申请日：2012-03-13

申请人： Il Young Han ,  Ho Geon Song ,  Sang Wook Park ,  Ji-Seok Hong

发明人： Il Young Han ,  Ho Geon Song ,  Sang Wook Park ,  Ji-Seok Hong

IPC分类号： B32B38/10

CPC分类号： H01L21/67092 ,  H01L21/6835 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/799 ,  H01L24/94 ,  H01L24/96 ,  H01L24/98 ,  H01L25/0652 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/7999 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  Y10T156/11 ,  Y10T156/19 ,  H01L2224/81 ,  H01L2924/00

摘要： A debonder to manufacture a semiconductor that includes: a stage to support a carrier wafer that is attached to a chip stack assembly by a temporary adhesive layer coated on the surface of the carrier wafer; a chuck arranged above the stage to selectively secure the chip stack assembly; a lifting unit to lift the chuck from the stage; a lateral driving unit to move the chuck laterally with respect to the stage; and a controller to control the lifting unit and the lateral driving unit.

摘要翻译： 一种制造半导体的剥离器，包括：支撑通过涂覆在载体晶片的表面上的临时粘合剂层附着到芯片堆叠组件的载体晶片的载物台; 卡盘，布置在平台上方以选择性地固定芯片堆叠组件; 提升装置，用于将卡盘从舞台上抬起; 横向驱动单元，用于相对于所述平台横向移动所述卡盘; 以及控制器，用于控制提升单元和横向驱动单元。

公开(公告)号：US20120199968A1

公开(公告)日：2012-08-09

申请号：US13348020

申请日：2012-01-11

申请人： Sang-wook PARK ,  Ho-geon Song ,  Kwang-yong LEE

发明人： Sang-wook PARK ,  Ho-geon Song ,  Kwang-yong LEE

IPC分类号： H01L23/498 ,  H01L23/48

CPC分类号： H01L25/16 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2225/1011 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00012

摘要： A semiconductor package and method of manufacturing thereof are provided. The package includes: a substrate; a first metal wire on a top surface of the substrate; a first semiconductor chip disposed on the substrate; a first insulation layer which covers the first semiconductor chip and at least a part of the substrate; a second metal wire formed on a top surface of the first insulation layer; a first via formed in the first insulation layer, wherein the first via electrically connects the second metal wire and the first metal wire; and a second semiconductor chip disposed on the second metal wire, wherein the second semiconductor chip is electrically connected to the second metal wire.

摘要翻译： 提供半导体封装及其制造方法。 该包装包括：基材; 在所述基板的顶表面上的第一金属线; 设置在所述基板上的第一半导体芯片; 覆盖所述第一半导体芯片和所述基板的至少一部分的第一绝缘层; 形成在所述第一绝缘层的顶表面上的第二金属线; 形成在所述第一绝缘层中的第一通孔，其中所述第一通孔电连接所述第二金属线和所述第一金属线; 以及设置在所述第二金属线上的第二半导体芯片，其中所述第二半导体芯片电连接到所述第二金属线。

公开(公告)号：US20110318887A1

公开(公告)日：2011-12-29

申请号：US13094216

申请日：2011-04-26

申请人： Jun-young Ko ,  Jae-yong Park ,  Heui-seog Kim ,  Ho-geon Song

发明人： Jun-young Ko ,  Jae-yong Park ,  Heui-seog Kim ,  Ho-geon Song

IPC分类号： H01L21/56

CPC分类号： H01L21/52 ,  H01L21/56 ,  H01L21/565 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2225/06562

摘要： A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding.

摘要翻译： 模制半导体封装的方法包括在设置在基板上的半导体芯片的顶表面上涂布液体模制树脂或将固体模塑树脂设置。 固体成型树脂可以包括粉末成型树脂或片状模塑树脂。 在半导体芯片的上表面上涂布有液态成型树脂的情况下，将基板安装在下模和上模之间，然后将熔融模制树脂填充在下模和上模之间的空间中。 在固体成形树脂设置在半导体芯片的顶面的情况下，将基板安装在下模上，然后将固体成型树脂加热熔融成具有流动性的液态成型树脂。 上模具安装在下模具上，熔融模塑树脂填充在下模和上模之间的空间中。

公开(公告)号：US20110136334A1

公开(公告)日：2011-06-09

申请号：US12903714

申请日：2010-10-13

申请人： Hwang-Bok Ryu ,  Ky-Hyun Jung ,  Jae-Yong Park ,  Ho-Geon Song

发明人： Hwang-Bok Ryu ,  Ky-Hyun Jung ,  Jae-Yong Park ,  Ho-Geon Song

IPC分类号： H01L21/60

CPC分类号： H01L24/85 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48599 ,  H01L2224/49 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A method of forming at least one bonding structure may be provided. A ball may be formed on the front end of a wire outside a capillary. The capillary may be moved downwardly to form a preliminary compressed ball on a first pad using the ball. The capillary may be moved upwardly to form a neck portion on the preliminary compressed ball using the preliminary compressed ball and the wire. The capillary may be moved obliquely and downwardly to form a compressed ball. The capillary may extend the wire from the compressed ball to a second pad.

摘要翻译： 可以提供形成至少一个结合结构的方法。 可以在毛细管外部的线的前端形成球。 毛细管可以向下移动以在使用球的第一垫上形成预压缩球。 毛细管可以向上移动，以便在预压缩球上形成颈部，使用预压缩球和线。 毛细管可以倾斜向下移动以形成压缩球。 毛细管可以将丝线从压缩球延伸到第二垫。

公开(公告)号：US20090134510A1

公开(公告)日：2009-05-28

申请号：US12209428

申请日：2008-09-12

申请人： Hak-Sung KIM ,  Ho-Geon Song ,  Seok-Won JEONG

发明人： Hak-Sung KIM ,  Ho-Geon Song ,  Seok-Won JEONG

IPC分类号： H01L23/528 ,  H01L21/768

CPC分类号： H01L25/105 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49827 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/07811 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor package and method of fabricating the same. The semiconductor package includes a first semiconductor package, a second semiconductor package stacked on the first semiconductor package, and a first electrical connector interposed between the first and second semiconductor packages to electrically connect the first and second semiconductor packages.

摘要翻译： 一种半导体封装及其制造方法。 半导体封装包括第一半导体封装，堆叠在第一半导体封装上的第二半导体封装，以及插入在第一和第二半导体封装之间以将第一和第二半导体封装电连接的第一电连接器。

公开(公告)号：US20070047377A1

公开(公告)日：2007-03-01

申请号：US11500960

申请日：2006-08-09

申请人： Hyo-Jae Bang ,  Dong-Chun Lee ,  Ho-Geon Song ,  Seong-Chan Han ,  Kwang-Su Yu ,  Dong-Woo Shin

发明人： Hyo-Jae Bang ,  Dong-Chun Lee ,  Ho-Geon Song ,  Seong-Chan Han ,  Kwang-Su Yu ,  Dong-Woo Shin

IPC分类号： G11C8/00

CPC分类号： H05K3/403 ,  H01L2224/48091 ,  H01L2224/4824 ,  H05K3/0052 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2201/0919 ,  H05K2203/1189 ,  H01L2924/00014

摘要： Example embodiments of the present invention may include a printed circuit board, a method of manufacturing the printed circuit board, and a memory module/socket assembly. Example embodiments of the present invention may increase the number of contact taps on a memory module, in addition, a force required to insert the memory module into a module socket may be decreased.

摘要翻译： 本发明的示例性实施例可以包括印刷电路板，制造印刷电路板的方法和存储器模块/插座组件。 本发明的示例实施例可以增加存储器模块上的接触抽头的数量，此外，可以减少将存储器模块插入模块插座所需的力。