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20 条记录 (耗时 0.051 秒)

    Packaging substrate and method of manufacturing the same
    2.
    发明申请
    Packaging substrate and method of manufacturing the same 审中-公开
    包装基材及其制造方法

    公开(公告)号：US20080044931A1

    公开(公告)日：2008-02-21

    申请号：US11646291

    申请日：2006-12-28

    申请人： Ho-Ming Tong ,  Kao-Ming Su ,  Chao-Fu Weng ,  Che-Ya Chou ,  Shin-Hua Chao ,  Teck-Chong Lee ,  Song-Fu Yang ,  Chian-Chi Lin

    发明人： Ho-Ming Tong ,  Kao-Ming Su ,  Chao-Fu Weng ,  Che-Ya Chou ,  Shin-Hua Chao ,  Teck-Chong Lee ,  Song-Fu Yang ,  Chian-Chi Lin

    IPC分类号： H01L21/98

    CPC分类号： H05K3/0052 ,  H01L21/485 ,  H01L24/97 ,  H01L24/98 ,  H01L25/50 ,  H05K3/225 ,  H05K2201/10598

    摘要： A packaging substrate and a method of manufacturing the same are provided. The method includes following steps. First, a first substrate including at least one defected packaging unit and several first packaging units is provided. The defected packaging unit and the first packaging units are arranged in an array on the first substrate. Next, the defected packaging unit is removed from the first substrate to correspondingly form at least one opening in the first substrate. Then, a second substrate including at least one second packaging unit is provided. Later, the second packaging unit is separated from the second substrate. The area of the second packaging unit is less than that of the opening. Subsequently, the second packaging unit is disposed in the opening. The edge of the second packaging unit is placed partially against an inner wall of the opening.

    摘要翻译： 提供了一种封装基板及其制造方法。 该方法包括以下步骤。 首先，提供包括至少一个缺陷包装单元和多个第一包装单元的第一基板。 缺陷包装单元和第一包装单元以阵列布置在第一基板上。 接下来，将缺陷的包装单元从第一基板移除，以相应地形成第一基板中的至少一个开口。 然后，提供包括至少一个第二包装单元的第二基板。 之后，第二包装单元与第二基板分离。 第二包装单元的面积小于开口面积。 随后，第二包装单元设置在开口中。 第二包装单元的边缘部分地放置在开口的内壁上。

    Stackable Package Having Embedded Interposer and Method for Making the Same
    8.
    发明申请
    Stackable Package Having Embedded Interposer and Method for Making the Same 审中-公开
    具有嵌入式内插器的可堆叠封装及其制作方法

    公开(公告)号：US20100289133A1

    公开(公告)日：2010-11-18

    申请号：US12727770

    申请日：2010-03-19

    申请人： Shin-Hua Chao ,  Teck-Chong Lee ,  Shing-Cheng Liang

    发明人： Shin-Hua Chao ,  Teck-Chong Lee ,  Shing-Cheng Liang

    IPC分类号： H01L23/488 ,  H01L21/60 ,  H01L23/498

    CPC分类号： H01L23/5389 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： The present invention relates to a stackable package having an embedded interposer and a method for making the same. The package includes a substrate, a chip, a first embedded interposer, a circuit layer and a solder mask. The substrate has an upper surface, a bottom surface and at least one connecting pad. The connecting pad is disposed adjacent to the upper surface. The chip is disposed adjacent to the upper surface of the substrate, and is electrically connected to the substrate. The first embedded interposer encapsulates the upper surface of the substrate and the chip. The to first embedded interposer includes at least one plating through hole. The plating through hole penetrates through the first embedded interposer, and is connected to the connecting pad of the substrate. The circuit layer is disposed adjacent to the first embedded interposer, and the plating through hole is connected to the circuit layer. The circuit layer includes at least one pad. The solder mask is disposed adjacent to the circuit layer, and exposes the pad. Therefore, the package has more pads for inputting/outputting, more flexibility for stacking a top package, and a reduced total thickness.

    摘要翻译： 本发明涉及具有嵌入式插入器的可堆叠封装及其制造方法。 封装包括衬底，芯片，第一嵌入式插入器，电路层和焊接掩模。 基板具有上表面，底表面和至少一个连接垫。 连接垫邻近上表面设置。 芯片靠近基板的上表面设置，并与基板电连接。 第一嵌入式插入器封装衬底和芯片的上表面。 第一嵌入式插入器包括至少一个电镀通孔。 电镀通孔穿过第一嵌入式插入器，并连接到衬底的连接焊盘。 电路层与第一嵌入式插入件相邻设置，电镀通孔与电路层连接。 电路层包括至少一个焊盘。 焊接掩模邻近电路层设置，并露出焊盘。 因此，封装具有更多的用于输入/输出的焊盘，用于堆叠顶部封装的更大的灵活性和更小的总厚度。

    MULTI-CHIP PACKAGE STRUCTURE
    10.
    发明申请
    MULTI-CHIP PACKAGE STRUCTURE 有权
    多芯片包装结构

    公开(公告)号：US20050199991A1

    公开(公告)日：2005-09-15

    申请号：US10904404

    申请日：2004-11-09

    申请人： Shin-Hua Chao ,  Jian-Wen Lo

    发明人： Shin-Hua Chao ,  Jian-Wen Lo

    IPC分类号： H01L23/48

    CPC分类号： H01L25/0652 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17505 ,  H01L2224/81986 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599

    摘要： A multi-chip package structure comprising a first chip, a patterned lamination layer, a plurality of first bumps, a second chip and second bumps is provided. The first chip has a first active surface. The patterned lamination layer is disposed on a portion area of the first active surface. The first chip has a plurality of first bonding pads disposed on the first active surface exposed by the patterned lamination layer and the patterned lamination layer has a plurality of second bonding pads disposed thereon. The second chip has a second active surface and the first bumps are disposed on the second active surface. The second chip is electrically connected to the first bonding pads through the first bumps. The second bumps are disposed on the second bonding pads. Moreover, the multi-chip package structure further comprises a component disposed on the first chip and electrically connects to the first bonding pads.

    摘要翻译： 提供了包括第一芯片，图案化层压层，多个第一凸块，第二芯片和第二凸块的多芯片封装结构。 第一芯片具有第一活性表面。 图案化层压层设置在第一活性表面的一部分区域上。 第一芯片具有多个第一接合焊盘，其设置在由图案化层压层暴露的第一有源表面上，并且图案化层叠层具有设置在其上的多个第二接合焊盘。 第二芯片具有第二有源表面，并且第一突起设置在第二有源表面上。 第二芯片通过第一凸块电连接到第一焊盘。 第二凸块设置在第二接合焊盘上。 此外，多芯片封装结构还包括设置在第一芯片上并与第一焊盘电连接的部件。